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numicro? nuc100 data sheet arm cortex?-m0 32-bit microcontroller publication release date: jan. 2, 2012 - 1 - revision v2.03 numicro? family nuc100 data sheet the information described in this document is the exclusive intellectual property of nuvoton technology corporation and shall not be reproduced without permission from nuvoton. nuvoton is providing this document only for reference purposes of numicro microcontroller based system design. nuvoton assumes no responsibility for errors or omissions. all data and specifications are subject to change without notice. for additional information or questions, please contact: nuvoton technology corporation.
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 2 - revision v2.03 contents 1 ? general description ......................................................................................................... 7 ? 2 ? features ................................................................................................................................. 8 ? 2.1 ? numicro ? nuc100 features ? advanced line .............................................................. 8 ? 3 ? parts information list and pin configuration .................................................... 12 ? 3.1 ? numicro ? nuc100 products selection guide ............................................................. 12 ? 3.1.1 ? numicro ? nuc100 medium density advance line selection guide .............................12 ? 3.1.2 ? numicro ? nuc100 low density advance line selection guide ...................................12 ? 3.2 ? pin configuration .......................................................................................................... 13 ? 3.2.1 ? numicro ? nuc100 medium density pin diagram .........................................................13 ? 3.2.2 ? numicro ? nuc100 low density pin diagram ...............................................................16 ? 4 ? block diagram .................................................................................................................... 18 ? 4.1 ? numicro ? nuc100 medium density block diagram ................................................... 18 ? 4.2 ? numicro ? nuc100 low density block diagram .......................................................... 19 ? 5 ? functional description .................................................................................................. 20 ? 5.1 ? arm ? cortex?-m0 core .............................................................................................. 20 ? 5.2 ? system manager ........................................................................................................... 22 ? 5.2.1 ? overview ........................................................................................................................22 ? 5.2.2 ? system reset .................................................................................................................22 ? 5.2.3 ? system power distribution .............................................................................................23 ? 5.2.4 ? system memory map ......................................................................................................24 ? 5.2.5 ? system timer (systick) .................................................................................................26 ? 5.2.6 ? nested vectored interrupt controller (nvic) ..................................................................27 ? 5.3 ? clock controller ............................................................................................................ 31 ? 5.3.1 ? overview ........................................................................................................................31 ? 5.3.2 ? clock generator .............................................................................................................33 ? 5.3.3 ? system clock and systick clock ...................................................................................34 ? 5.3.4 ? peripherals clock ...........................................................................................................35 ? 5.3.5 ? power down mode clock ...............................................................................................35 ? 5.3.6 ? frequency divider output ...............................................................................................36 ? 5.4 ? general purpose i/o (gpio) ........................................................................................ 37 ? 5.4.1 ? overview ........................................................................................................................37 ? 5.4.2 ? features .........................................................................................................................37 ? 5.5 ? i 2 c serial interface controller (master/slave) (i 2 c) ...................................................... 38 ? 5.5.1 ? overview ........................................................................................................................38 ? 5.5.2 ? features .........................................................................................................................39 ? 5.6 ? pwm generator and capture timer (pwm) ................................................................ 40 ? 5.6.1 ? overview ........................................................................................................................40 ? 5.6.2 ? features .........................................................................................................................41 ? 5.7 ? real time clock (rtc) ................................................................................................. 42 ? 5.7.1 ? overview ........................................................................................................................42 ?
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 3 - revision v2.03 5.7.2 ? features .........................................................................................................................42 ? 5.8 ? serial peripheral interface (spi) ................................................................................... 43 ? 5.8.1 ? overview ........................................................................................................................43 ? 5.8.2 ? features .........................................................................................................................43 ? 5.9 ? timer controller (tmr) ................................................................................................. 44 ? 5.9.1 ? overview ........................................................................................................................44 ? 5.9.2 ? features .........................................................................................................................44 ? 5.10 ? watchdog timer (wdt) ................................................................................................ 45 ? 5.10.1 ? overview ......................................................................................................................45 ? 5.10.2 ? features .......................................................................................................................47 ? 5.11 ? uart interface controller (uart) ............................................................................... 47 ? 5.11.1 ? overview ......................................................................................................................47 ? 5.11.2 ? features .......................................................................................................................49 ? 5.12 ? ps/2 device controller (ps2d) ..................................................................................... 50 ? 5.12.1 ? overview ......................................................................................................................50 ? 5.12.2 ? features .......................................................................................................................50 ? 5.13 ? i 2 s controller (i 2 s)......................................................................................................... 51 ? 5.13.1 ? overview ......................................................................................................................51 ? 5.13.2 ? features .......................................................................................................................51 ? 5.14 ? analog-to-digital converter (adc) ............................................................................... 52 ? 5.14.1 ? overview ......................................................................................................................52 ? 5.14.2 ? features .......................................................................................................................52 ? 5.15 ? analog comparator (cmp) ........................................................................................... 53 ? 5.15.1 ? overview ......................................................................................................................53 ? 5.15.2 ? features .......................................................................................................................53 ? 5.16 ? pdma controller (pdma) ............................................................................................. 54 ? 5.16.1 ? overview ......................................................................................................................54 ? 5.16.2 ? features .......................................................................................................................54 ? 5.17 ? external bus interface (ebi) ......................................................................................... 55 ? 5.17.1 ? overview ......................................................................................................................55 ? 5.17.2 ? features .......................................................................................................................55 ? 6 ? flash memory controller (fmc) ................................................................................ 56 ? 6.1 ? overview ....................................................................................................................... 56 ? 6.2 ? features ........................................................................................................................ 56 ? 7 ? electrical characteristics ......................................................................................... 57 ? 7.1 ? absolute maximum ratings .......................................................................................... 57 ? 7.2 ? dc electrical characteristics ........................................................................................ 58 ? 7.2.1 ? numicro ? nuc100/nuc120 medium density dc electrical characteristics .................58 ? 7.2.2 ? numicro ? nuc100/nuc120 low density dc electrical characteristics .......................63 ? 7.2.3 ? operating current curve (test condition: run nop) .......................................................68 ? 7.2.4 ? idle current curve ..........................................................................................................70 ? 7.2.5 ? power down current curve ............................................................................................72 ?
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 4 - revision v2.03 7.3 ? ac electrical characteristics ........................................................................................ 73 ? 7.3.1 ? external 4~24 mhz high speed crystal .........................................................................73 ? 7.3.2 ? external 32.768 khz low speed crystal ........................................................................74 ? 7.3.3 ? internal 22.1184 mhz high speed oscillator ..................................................................74 ? 7.3.4 ? internal 10 khz low speed oscillator .............................................................................74 ? 7.4 ? analog characteristics .................................................................................................. 75 ? 7.4.1 ? specification of 12-bit saradc .....................................................................................75 ? 7.4.2 ? specification of ldo and power management ...............................................................76 ? 7.4.3 ? specification of low voltage reset ................................................................................77 ? 7.4.4 ? specification of brown-out detector ...............................................................................77 ? 7.4.5 ? specification of power-on reset (5 v) ...........................................................................77 ? 7.4.6 ? specification of temperature sensor .............................................................................78 ? 7.4.7 ? specification of comparator ...........................................................................................78 ? 7.5 ? flash dc electrical characteristics .............................................................................. 79 ? 7.6 ? spi dynamic characteristics ........................................................................................ 80 ? 8 ? package dimensions ......................................................................................................... 82 ? 8.1 ? 100l lqfp (14x14x1.4 mm footprint 2.0mm) .............................................................. 82 ? 8.2 ? 64l lqfp (10x10x1.4mm footprint 2.0 mm) ................................................................ 83 ? 8.3 ? 48l lqfp (7x7x1.4mm footprint 2.0mm) ..................................................................... 84 ? 9 ? revision history ................................................................................................................ 85 ?
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 5 - revision v2.03 figures figure 3-1 numicro ? nuc100 medium density lqfp 100-pin pin diagram ............................... 13 ? figure 3-2 numicro ? nuc100 medium density lqfp 64-pin pin diagram ................................. 14 ? figure 3-3 numicro ? nuc100 medium density lqfp 48-pin pin diagram ................................. 15 ? figure 3-4 numicro ? nuc100 low density lqfp 64-pin pin diagram ........................................ 16 ? figure 3-5 numicro ? nuc100 low density lqfp 48-pin pin diagram ........................................ 17 ? figure 4-1 numicro ? nuc100 medium density block diagram ................................................... 18 ? figure 4-2 numicro ? nuc100 low density block diagram ......................................................... 19 ? figure 5-1 functional controller diagram ...................................................................................... 20 ? figure 5-3 numicro ? nuc100 power distribution diagram .......................................................... 23 ? figure 5-4 clock generator global view diagram ........................................................................... 32 ? figure 5-5 clock generator block diagram ..................................................................................... 33 ? figure 5-6 system clock block diagram ....................................................................................... 34 ? figure 5-7 systick clock control block diagram .......................................................................... 34 ? figure 5-8 clock source of frequency divider .............................................................................. 36 ? figure 5-9 block diagram of frequency divider ............................................................................ 36 ? figure 5-10 i 2 c bus timing ............................................................................................................ 38 ? figure 5-11 timing of interrupt and reset signal .......................................................................... 46 ? figure 7-1 typical crystal application circuit ................................................................................ 74 ? figure 7-2 spi master dynamic characteristics timing ................................................................... 81 ? figure 7-3 spi slave dynamic characteristics timing ..................................................................... 81 ?
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 6 - revision v2.03 tables table 1-1 connectivity supported table .......................................................................................... 7 ? table 5-1 address space assignments for on-chip controllers ................................................... 25 ? table 5-2 exception model ............................................................................................................ 28 ? table 5-3 system interrupt map ..................................................................................................... 29 ? table 5-4 vector table format ...................................................................................................... 30 ? table 5-5 watchdog timeout interval selection ............................................................................ 45 ? table 5-6 uart baud rate equation ............................................................................................ 47 ? table 5-7 uart baud rate setting table ..................................................................................... 48 ?
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 7 - revision v2.03 1 general description the numicro ? nuc100 series is 32-bit microcontrollers with embedded arm ? cortex?-m0 core for industrial control and applications which need rich communication interfaces. the cortex?-m0 is the newest arm ? embedded processor with 32-bit performance and at a cost equivalent to traditional 8-bit microcontroller. numicro ? nuc100 series includes nuc100, nuc120, nuc130 and nuc140 product line. the numicro ? nuc100 advanced line embeds cortex?- m0 core running up to 50 mhz with 32k/64k/128k-byte embedded flash, 4k/8k/16k -byte embedded sram, and 4k-byte loader rom for the isp. it also equips with plenty of peripheral devices, such as timers, watchdog timer, rtc, pdma, uart, spi, i 2 c, i 2 s, pwm timer, gpio, ps/2, 12-bit adc, analog comparator, low voltage reset controller and brown-out detector. product line uart spi i 2 c usb lin can ps/2 i 2 s nuc100 nuc120 nuc130 nuc140 table 1-1 connectivity supported table
numicro? nuc100 data sheet 2 features the equipped features are dependent on the product line and their sub products. 2.1 numicro ? nuc100 features ? advanced line ? core C arm ? cortex?-m0 core runs up to 50 mhz C one 24-bit system timer C supports low power sleep mode C single-cycle 32-bit hardware multiplier C nvic for the 32 interrupt inputs, each with 4-levels of priority C serial wire debug supports with 2 watchpoints/4 breakpoints ? build-in ldo for wide operating voltage ranges from 2.5 v to 5.5 v ? flash memory C 32k/64k/128k bytes flash for program code (128kb only support in numicro ? nuc100/nuc120 medium density) C 4kb flash for isp loader C support in-system program (isp) application code update C 512 byte page erase for flash C configurable data flash address and size for 128kb system, fixed 4kb data flash for the 32kb and 64kb system C support 2 wire icp update through swd/ice interface C support fast parallel programming mode by external programmer ? sram memory C 4k/8k/16k bytes embedded sram (16kb only support in numicro ? nuc100/nuc120 medium density) C support pdma mode ? pdma (peripheral dma) C support 9 channels pdma for automatic dat a transfer between sram and peripherals (only support 1 channel in numicro ? nuc100/nuc120 low density) ? clock control C flexible selection for different applications C built-in 22.1184 mhz high speed osc for system operation ? trimmed to 1 % at +25 and v dd = 5 v ? trimmed to 3 % at -40 ~ +85 and v dd = 2.5 v ~ 5.5 v C built-in 10 khz low speed osc for watchdog timer and wake-up operation C support one pll, up to 50 mhz, for high performance system operation C external 4~24 mhz high speed crystal input for precise timing operation C external 32.768 khz low speed crystal input for rtc function and low power system operation ? gpio C four i/o modes: ? quasi bi-direction ? push-pull output ? open-drain output ? input only with high impendence publication release date: jan. 2, 2012 - 8 - revision v2.03
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 9 - revision v2.03 C ttl/schmitt trigger input selectable C i/o pin can be configured as interr upt source with edge/level setting C high driver and high sink io mode support ? timer C support 4 sets of 32-bit timers with 24-b it up-timer and one 8-bit pre-scale counter C independent clock source for each timer C provides one-shot, periodic, toggle and continuous counting operation modes (numicro ? nuc100/nuc120 medium density only support one-shot and periodic mode) C support event counting function ( numicro ? nuc100/nuc120 low density only ) ? watchdog timer C multiple clock sources C 8 selectable time out period from 1.6ms ~ 26.0sec (depends on clock source) C wdt can wake-up from power down or idle mode C interrupt or reset select able on watchdog time-out ? rtc C support software compensation by setting frequency compensate register (fcr) C support rtc counter (second, minute, hour ) and calendar counter (day, month, year) C support alarm registers (second, minute, hour, day, month, year) C selectable 12-hour or 24-hour mode C automatic leap year recognition C support periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second C support wake-up function ? pwm/capture C built-in up to four 16-bit pwm generator s provide eight pwm outputs or four complementary paired pwm outputs C each pwm generator equipped with one clock source selector, one clock divider, one 8-bit prescaler and one dead-zone generator for complementary paired pwm C up to eight 16-bit digital capture timers (shared with pwm timers) provide eight rising/falling capture inputs C support capture interrupt ? uart C up to three uart controllers (numicro ? nuc100/nuc120 low density only support 2 uart controllers) C uart ports with flow control (txd, rxd, cts and rts) C uart0 with 63-byte fifo is for high speed C uart1/2(optional) with 15-byte fifo for standard device C support irda (sir) function C support rs-485 9-bit mode and direction control. (numicro ? nuc100/nuc120 low density only) C programmable baud-rate generator up to 1/16 system clock C support pdma mode ? spi C up to four sets of spi controller (numicro ? nuc100/nuc120 low density only support 2 spi controllers) C master up to 16 mhz, and slave up to 10 mhz (chip working @ 5v) C support spi master/slave mode
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 10 - revision v2.03 C full duplex synchronous serial data transfer C variable length of transfer data from 1 to 32 bits C msb or lsb first data transfer C rx and tx on both rising or falling edge of serial clock independently C 2 slave/device select lines when it is as the master, and 1 slave/device select line when it is as the slave C support byte suspend mode in 32-bit transmission C support pdma mode ? i 2 c C up to two sets of i 2 c device C master/slave mode C bidirectional data transfer between masters and slaves C multi-master bus (no central master) C arbitration between simultaneously transmitti ng masters without co rruption of serial data on the bus C serial clock synchronization allows devices with different bit rates to communicate via one serial bus C serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer C programmable clocks allow versatile rate control C support multiple address recognition (fou r slave address with mask option) ? i 2 s C interface with external audio codec C operate as either master or slave mode C capable of handling 8-, 16-, 24- and 32-bit word sizes C mono and stereo audio data supported C i 2 s and msb justified data format supported C two 8 word fifo data buffers are provided, one for transmit and one for receive C generates interrupt requests when buffer levels cross a programmable boundary C support two dma requests, one for transmit and one for receive ? ps/2 device controller C host communication inhibit and request to send detection C reception frame error detection C programmable 1 to 16 bytes transmit buffer to reduce cpu intervention C double buffer for data reception C s/w override bus ? ebi (external bus inte rface) support (numicro ? nuc100/nuc120 low density 64-pin package only) C accessible space: 64kb in 8-bit mode or 128kb in 16-bit mode C support 8-/16-bit data width C support byte write in 16-bit data width mode ? adc C 12-bit sar adc with 600k sps C up to 8-ch single-end input or 4-ch differential input C single scan/single cycle scan/continuous scan C each channel with individual result register C scan on enabled channels C threshold voltage detection C conversion start by software programming or external input C support pdma mode
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 11 - revision v2.03 ? analog comparator C up to two analog comparators C external input or internal bandgap voltage selectable at negative node C interrupt when compare result change C power down wake-up ? one built-in temperature sensor with 1 resolution ? brown-out detector C with 4 levels: 4.5 v/3.8 v/2.7 v/2.2 v C support brown-out interrupt and reset option ? low voltage reset C threshold voltage levels: 2.0 v ? operating temperature: -40 ~85 ? packages: C all green package (rohs) C lqfp 100-pin / 64-pin / 48-pin (100-pin for numicro ? nuc100/nuc120 medium density only)
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 12 - revision v2.03 3 parts information list and pin configuration 3.1 numicro ? nuc100 products selection guide 3.1.1 numicro ? nuc100 medium density advance line selection guide connectivity part number aprom ram data flash isp loader rom i/o timer uart spi i 2 c usb lin can i 2 s comp. pwm adc rtc ebi isp icp package nuc100ld3an 64 kb 16 kb 4 kb 4 kb up to 35 4x32-bit 2 1 2 - - - 1 1 6 8x12-bit v - v lqfp48 nuc100le3an 128 kb 16 kb definable 4 kb up to 35 4x32-bit 2 1 2 - - - 1 1 6 8x12-bit v - v lqfp48 nuc100rd3an 64 kb 16 kb 4 kb 4 kb up to 49 4x32-bit 3 2 2 - - - 1 2 6 8x12-bit v - v lqfp64 NUC100RE3AN 128 kb 16 kb definable 4 kb up to 49 4x32-bit 3 2 2 - - - 1 2 6 8x12-bit v - v lqfp64 nuc100vd2an 64 kb 8 kb 4 kb 4 kb up to 80 4x32-bit 3 4 2 - - - 1 2 8 8x12-bit v - v lqfp100 nuc100vd3an 64 kb 16 kb 4 kb 4 kb up to 80 4x32-bit 3 4 2 - - - 1 2 8 8x12-bit v - v lqfp100 nuc100ve3an 128 kb 16 kb definable 4 kb up to 80 4x32-bit 3 4 2 - - - 1 2 8 8x12-bit v - v lqfp100 3.1.2 numicro ? nuc100 low density advance line selection guide connectivity part number aprom ram data flash isp loader rom i/o timer uart spi i 2 c usb lin can i 2 s comp. pwm adc rtc ebi isp icp package nuc100lc1bn 32 kb 4 kb 4 kb 4 kb up to 35 4x32-bit 2 1 2 - - - 1 1 4 8x12-bit v - v lqfp48 nuc100ld1bn 64 kb 4 kb 4 kb 4 kb up to 35 4x32-bit 2 1 2 - - - 1 1 4 8x12-bit v - v lqfp48 nuc100ld2bn 64 kb 8 kb 4 kb 4 kb up to 35 4x32-bit 2 1 2 - - - 1 1 4 8x12-bit v - v lqfp48 nuc100rc1bn 32 kb 4 kb 4 kb 4 kb up to 49 4x32-bit 2 2 2 - - - 1 2 4 8x12-bit v v v lqfp64 nuc100rd1bn 64 kb 4 kb 4 kb 4 kb up to 49 4x32-bit 2 2 2 - - - 1 2 4 8x12-bit v v v lqfp64 nuc100rd2bn 64 kb 8 kb 4 kb 4 kb up to 49 4x32-bit 2 2 2 - - - 1 2 4 8x12-bit v v v lqfp64
numicro? nuc100 data sheet 3.2 pin configuration 3.2.1 numicro ? nuc100 medium density pin diagram 3.2.1.1 numicro ? nuc100 medium density lqfp 100 pin adc5/pa.5 adc6/pa.6 adc7/spiss21/pa.7 spiss31/int0/pb.14 cpo1/pb.13 clko/cpo0/pb.12 x32i x32o i2c1scl/pa.11 i2c1sda/pa.10 i2c0scl/pa.9 i2c0sda/pa.8 rxd1/pb.4 txd1/pb.5 rts1/pb.6 cts1/pb.7 ldo v dd v ss cpn0/pc.7 cpp0/pc.6 cpn1/pc.15 cpp1/pc.14 int1/pb.15 xt1_out xt1_in /reset stadc/pb.8 pa.4/adc4 pa.3/adc3 pa.2/adc2 pa.1/adc1 pa.0/adc0 av ss ice_ck ice_dat pa.12/pwm0 pa.13/pwm1 pa.14/pwm2 pa.15/pwm3/i2smclk pc.8/spiss10 pc.9/spiclk1 av dd v ss v dd pv ss pc.0/spiss00/i2slrclk pc.1/spiclk0/i2sbclk pc.2/miso00/i2sdi pc.3/mosi00/i2sdo pd.15/txd2 pd.14/rxd2 pd.7 pd.6 pb.3/cts0 pb.2/rts0 pb.1/txd0 pb.0/rxd0 pe.7 pe.8 pe.9 pe.10 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 pc.10/miso10 pc.11/mosi10 nuc100vxxan medium density lqfp 100-pin 25 24 23 22 21 20 19 18 17 pe.15 pe.14 pe.13 spiss30/pd.8 spiclk3/pd.9 miso30/pd.10 mosi30/pd.11 miso31/pd.12 mosi31/pd.13 42 43 44 45 46 47 48 49 50 pe.11 pe.12 pc.4/miso01 pc.5/mosi01 pb.9/spiss11 pb.10/spiss01 pb.11/pwm4 pe.5/pwm5 pe.6 51 52 53 54 55 56 57 58 59 v ss v dd pc.12/miso11 pc.13/mosi11 pe.0/pwm6 pe.1/pwm7 pe.2 pe.3 pe.4 84 83 82 81 80 79 78 77 76 ps2dat ps2clk spiss20/pd.0 spiclk2/pd.1 miso20/pd.2 mosi20/pd.3 miso21/pd.4 mosi21/pd.5 v ref figure 3-1 numicro ? nuc100 medium density lqfp 100-pin pin diagram publication release date: jan. 2, 2012 - 13 - revision v2.03
numicro? nuc100 data sheet 3.2.1.2 numicro ? nuc100 medium density lqfp 64 pin adc5/pa.5 adc6/pa.6 adc7/pa.7 int0/pb.14 cpo1/pb.13 clko/cpo0/pb.12 x32i x32o i2c1scl/pa.11 i2c1sda/pa.10 i2c0scl/pa.9 i2c0sda/pa.8 rxd1/pb.4 txd1/pb.5 rts1/pb.6 cts1/pb.7 ldo v dd v ss cpn0/pc.7 cpp0/pc.6 cpn1/pc.15 cpp1/pc.14 int1/pb.15 xt1_out xt1_in /reset stadc/pb.8 pa.4/adc4 pa.3/adc3 pa.2/adc2 pa.1/adc1 pa.0/adc0 av ss ice_ck ice_dat pa.12/pwm0 pa.13/pwm1 pa.14/pwm2 pa.15/pwm3/i2smclk pc.8/spiss10 pc.9/spiclk1 av dd v ss v dd pv ss pc.0/spiss00/i2slrclk pc.1/spiclk0/i2sbclk pc.2/miso00/i2sdi pc.3/mosi00/i2sdo 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 pc.10/miso10 pc.11/mosi10 pb.9 pb.10 pb.11/pwm4 pe.5/pwm5 pd.15/txd2 pd.14/rxd2 pd.7 pd.6 pb.3/cts0 pb.2/rts0 pb.1/txd0 pb.0/rxd0 nuc100rxxan medium density lqfp 64-pin figure 3-2 numicro ? nuc100 medium density lqfp 64-pin pin diagram publication release date: jan. 2, 2012 - 14 - revision v2.03
numicro? nuc100 data sheet 3.2.1.3 numicro ? nuc100 medium density lqfp 48 pin clko/cpo0/pb.12 x32i x32o i2c1scl/pa.11 i2c1sda/pa.10 i2c0scl/pa.9 i2c0sda/pa.8 rxd1/pb.4 txd1/pb.5 ldo v dd v ss pa.4/adc4 pa.3/adc3 pa.2/adc2 pa.1/adc1 pa.0/adc0 av ss ice_ck ice_dat pa.12/pwm0 pa.13/pwm1 pa.14/pwm2 pa.15/pwm3/i2smclk 12 11 10 9 8 7 6 5 4 3 2 1 25 26 27 28 29 30 31 32 33 34 35 36 figure 3-3 numicro ? nuc100 medium density lqfp 48-pin pin diagram publication release date: jan. 2, 2012 - 15 - revision v2.03
numicro? nuc100 data sheet 3.2.2 numicro ? nuc100 low density pin diagram 3.2.2.1 numicro ? nuc100 low density lqfp 64 pin ad8/adc5/pa.5 ad7/adc6/pa.6 ad6/adc7/pa.7 int0/pb.14 ad1/cpo1/pb.13 ad0/clko/cpo0/pb.12 x32i x32o nrd/i2c1scl/pa.11 nwr/i2c1sda/pa.10 i2c0scl/pa.9 i2c0sda/pa.8 rxd1/pb.4 txd1/pb.5 ale/rts1/pb.6 ncs/cts1/pb.7 ldo v dd v ss ad5/cpn0/pc.7 ad4/cpp0/pc.6 ad3/cpn1/pc.15 ad2/cpp1/pc.14 int1/pb.15 xt1_out xt1_in /reset stadc/tm0/pb.8 pa.4/adc4/ad9 pa.3/adc3/ad10 pa.2/adc2/ad11 pa.1/adc1/ad12 pa.0/adc0 av ss ice_ck ice_dat pa.12/pwm0/ad13 pa.13/pwm1/ad14 pa.14/pwm2/ad15 pa.15/pwm3/i2smclk pc.8/spiss10/mclk pc.9/spiclk1 av dd v ss v dd pv ss pc.0/spiss00/i2slrclk pc.1/spiclk0/i2sbclk pc.2/miso00/i2sdi pc.3/mosi00/i2sdo 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 pc.10/miso10 pc.11/mosi10 pb.9/tm1 pb.10/tm2 pb.11/tm3 pe.5 pd.15 pd.14 pd.7 pd.6 pb.3/cts0/nwrh pb.2/rts0/nwrl pb.1/txd0 pb.0/rxd0 nuc100rxxbn low density lqfp 64-pin figure 3-4 numicro ? nuc100 low density lqfp 64-pin pin diagram publication release date: jan. 2, 2012 - 16 - revision v2.03
numicro? nuc100 data sheet 3.2.2.2 numicro ? nuc100 low density lqfp 48 pin clko/cpo0/pb.12 x32i x32o i2c1scl/pa.11 i2c1sda/pa.10 i2c0scl/pa.9 i2c0sda/pa.8 rxd1/pb.4 txd1/pb.5 ldo v dd v ss pa.4/adc4 pa.3/adc3 pa.2/adc2 pa.1/adc1 pa.0/adc0 av ss ice_ck ice_dat pa.12/pwm0 pa.13/pwm1 pa.14/pwm2 pa.15/pwm3/i2smclk 12 11 10 9 8 7 6 5 4 3 2 1 25 26 27 28 29 30 31 32 33 34 35 36 figure 3-5 numicro ? nuc100 low density lqfp 48-pin pin diagram publication release date: jan. 2, 2012 - 17 - revision v2.03
numicro? nuc100 data sheet 4 block diagram 4.1 numicro ? nuc100 medium density block diagram flash 128kb cortex-m0 50mhz clk_ctl pdma isp 4kb sram 16kb gpio a,b,c,d,e uart 1 -115k i2c 1 timer 2/3 rtc wdt i2c 0 spi 0/1 uart 0 -3m pwm 0~3 timer 0/1/ 12-bit adc analog comparator por brown-out lvr peripherals with pdma i2s 10 khz 32.768 khz p l l 22.1184 mhz 4~24 mhz ldo 2.5v~ 5.5v pwm 4~7 uart 2 -115k spi 2/3 ps2 figure 4-1 numicro ? nuc100 medium density block diagram publication release date: jan. 2, 2012 - 18 - revision v2.03
numicro? nuc100 data sheet 4.2 numicro ? nuc100 low density block diagram flash 64kb cortex-m0 50mhz clk_ctl pdma isp 4kb sram 8kb gpio a,b,c,d,e uart 1 -115k i2c 1 timer 2/3 rtc wdt i2c 0 spi 0/1 uart 0 -3m pwm 0~3 timer 0/1/ 12-bit adc analog comparator por brown-out lvr peripherals with pdma i2s p l l ldo 2.5v~ 5.5v 10 khz 32.768 khz 22.1184 mhz 4~24 mhz figure 4-2 numicro ? nuc100 low density block diagram publication release date: jan. 2, 2012 - 19 - revision v2.03
numicro? nuc100 data sheet 5 functional description 5.1 arm ? cortex?-m0 core the cortex?-m0 processor is a configurable, mult istage, 32-bit risc processor. it has an amba ahb-lite interface and includes an nvic co mponent. it also has optional hardware debug functionality. the processor can execute thum b code and is compatible with other cortex-m profile processor. the profile supports two modes -thread mode and handler mode. handler mode is entered as a result of an exception. an exception return can only be issued in handler mode. thread mode is entered on reset, and can be entered as a result of an exception return. figure 5-1 shows the functional controller of processor. cortex-m0 processor core nested vectored interrupt controller (nvic) breakpoint and watchpoint unit debugger interface bus matrix debug access port (dap) debug cortex-m0 processor cortex-m0 components wakeup interrupt controller (wic) interrupts serial wire or jtag debug port ahb-lite interface figure 5-1 functional controller diagram the implemented device provides: sor that features: et systick timer ts little-endian data accesses dling bandoned and ption model. this is the armv6-m, terrupt (wfi), wait for event z a low gate count proces ? the armv6-m thumb? instruction s ? thumb-2 technology ? armv6-m compliant 24 -bit ? a 32-bit hardware multiplier ? the system interface suppor ? the ability to have deterministic, fixed-latency, interrupt han ? load/store-multiples and multicycle-multiplies that can be a restarted to facilitate rapid interrupt handling ? c application binary interface compliant exce c application binary interface (c-abi) compliant exception model that enables the use of pure c functions as interrupt handlers ? low power sleep mode entry using wait for in ( wfe) instructions, or the return from interrupt sleep-on-exit feature publication release date: jan. 2, 2012 - 20 - revision v2.03
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 21 - revision v2.03 z rrupt inputs, each with four levels of priority ive interrupt lines p mode z breakpoints. pling register (pcs r) for non-intrusive code profiling. mba-3 ahb-lite system inte rface that provides simple integration e dap (debug access port). nvic that features: ? 32 external inte ? dedicated non-maskable interrupt (nmi) input. ? support for both level-sensitive and pulse-sensit ? wake-up interrupt controller (wic), pr oviding ultra-low power slee s upport. debug support ? four hardware ? two watchpoints. ? program counter sam ? single step and vector catch capabilities. z bus interfaces: ? single 32-bit a t o all system peripherals and memory. ? single 32-bit slave port that supports th
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 22 - revision v2.03 5.2 system manager 5.2.1 overview system management includes these following sections: z system resets z system memory map z system management registers for part number id, chip reset and on-chip controllers reset , multi-functional pin control z system timer (systick) z nested vectored interrupt controller (nvic) z system control registers 5.2.2 system reset the system reset can be issued by one of the below listed events. for these reset event flags can be read by rstsrc register. z the power-on reset z the low level on the /reset pin z watchdog time out reset z low voltage reset z brown-out detector reset z cpu reset z system reset system reset and power-on reset all reset the whole chip including all peripherals. the difference between system reset and power-on reset is external crystal circuit and ispcon.bs bit. system reset doesn?t reset external crystal circuit and ispcon.bs bit, but power-on reset does.
numicro? nuc100 data sheet 5.2.3 system power distribution in this chip, the power distribution is divided into three segments. z analog power from av dd and av ss provides the power for analog components operation. z digital power from v dd and v ss supplies the power to the internal regulator which provides a fixed 2.5 v power for digital operation and i/o pins. the outputs of internal voltage regulators, ldo and v dd33 , require an external capacitor which should be located close to the corresponding pin. analog power (av dd ) should be the same voltage level of the digital power (v dd ). figure 5-2 shows the power distribution of numicro ? nuc100. 5v to 2.5v ldo pll 12-bit sar-adc brown out detector por50 por25 low voltage reset external 32.768 khz crystal analog comparator temperature seneor flash digital logic 2.5v internal 22.1184 mhz & 10 khz oscillator av dd av ss ldo 1uf io cell gpio nuc100 power distribution figure 5-2 numicro ? nuc100 power distribution diagram publication release date: jan. 2, 2012 - 23 - revision v2.03
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 24 - revision v2.03 5.2.4 system memory map numicro ? nuc100 series provides 4g-byte addressi ng space. the memory locations assigned to each on-chip controllers are shown in the fo llowing table. the detailed register definition, memory space, and programming detailed will be described in the following sections for each on- chip peripherals. numicro ? nuc100 series only supports little-endian data format. address space token controllers flash and sram memory space 0x0000_0000 ? 0x0001_ffff flash_ba flash memory space (128kb) 0x2000_0000 ? 0x2000_3fff sram_ba sram memory space (16kb) 0x6000_0000 ? 0x6001_ffff extmem_ba external memory space (128kb) (numicro ? nuc100/nuc120 low density 64-pin only) ahb controllers space (0x5000_0000 ? 0x501f_ffff) 0x5000_0000 ? 0x5000_01ff gcr_ba syst em global control registers 0x5000_0200 ? 0x5000_02ff clk_ba clock control registers 0x5000_0300 ? 0x5000_03ff int_ba interrupt multiplexer control registers 0x5000_4000 ? 0x5000_7fff gpio_ba gpio control registers 0x5000_8000 ? 0x5000_bfff pdma_ba peripheral dma control registers 0x5000_c000 ? 0x5000_ffff fmc_ba flash memory control registers 0x5001_0000 ? 0x5001_03ff ebi_ba external bus interface control registers (numicro ? nuc100/nuc120 low density 64-pin only) apb1 controllers space (0x4000_0000 ~ 0x400f_ffff) 0x4000_4000 ? 0x4000_7fff wdt_ba wa tchdog timer control registers 0x4000_8000 ? 0x4000_bfff rtc_ba real time clock (rtc) control register 0x4001_0000 ? 0x4001_3fff tmr01_ba timer0/timer1 control registers 0x4002_0000 ? 0x4002_3fff i2c0_ba i 2 c0 interface control registers 0x4003_0000 ? 0x4003_3fff spi0_ba spi0 with master/slave function control registers 0x4003_4000 ? 0x4003_7fff spi1_ba spi1 with master/slave function control registers 0x4004_0000 ? 0x4004_3fff pwma_ba pwm0/1/2/3 control registers 0x4005_0000 ? 0x4005_3fff uart0_ba uart0 control registers 0x4006_0000 ? 0x4006_3fff usbd_ba usb 2.0 fs device controller registers 0x400d_0000 ? 0x400d_3fff acmp_ba analog comparator control registers
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 25 - revision v2.03 address space token controllers 0x400e_0000 ? 0x400e_ffff adc_ba analog-digital-converter (adc) control registers apb2 controllers space (0x4010_0000 ~ 0x401f_ffff) 0x4010_0000 ? 0x4010_3fff ps2_ba ps/2 interface control registers 0x4011_0000 ? 0x4011_3fff tmr23_ba timer2/timer3 control registers 0x4012_0000 ? 0x4012_3fff i2c1_ba i 2 c1 interface control registers 0x4013_0000 ? 0x4013_3fff spi2_ba spi2 with master/slave function control registers ( numicro ? nuc100/nuc120 medium density only) 0x4013_4000 ? 0x4013_7fff spi3_ba spi3 with master/slave function control registers ( numicro ? nuc100/nuc120 medium density only) 0x4014_0000 ? 0x4014_3fff pwmb_ba pwm4/5/6/7 control registers ( numicro ? nuc100/nuc120 medium density only) 0x4015_0000 ? 0x4015_3fff uart1_ba uart1 control registers 0x4015_4000 ? 0x4015_7fff uart2_ba uart2 control registers ( numicro ? nuc100/nuc120 medium density only) 0x401a_0000 ? 0x401a_3fff i2s_ba i 2 s interface control registers system controllers space (0xe000_e000 ~ 0xe000_efff) 0xe000_e010 ? 0xe000_e0ff scs_ba system timer control registers 0xe000_e100 ? 0xe000_ecff scs_ba external interrupt controller control registers 0xe000_ed00 ? 0xe000_ed8f scs_ba system control registers table 5-1 address space assignments for on-chip controllers
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 26 - revision v2.03 5.2.5 system timer (systick) the cortex-m0 includes an integrated system time r, systick. systick pr ovides a simple, 24-bit clear-on-write, decrementing, wr ap-on-zero counter with a flexible control mechanism. the counter can be used as a real time operating sy stem (rtos) tick timer or as a simple counter. when system timer is enabled, it will count down from the value in the systick current value register (syst_cvr) to zero, and reload (wrap) to the value in the systick reload value register (syst_rvr) on the nex t clock cycle, then decrement on subsequent clocks. when the counter transitions to zero, the countflag st atus bit is set. the countflag bit clears on reads. the syst_cvr value is unknown on reset. software should write to the register to clear it to zero before enabling the feature. this ensures the timer will count fr om the syst_rvr value rather than an arbitrary value when it is enabled. if the syst_rvr is zero, the timer will be maintai ned with a current value of zero after it is reloaded with this value. this mechanism can be used to disable the feature independently from the timer enable bit. for more detailed information, please refer to the documents ?arm ? cortex?-m0 technical reference manual? and ?arm ? v6-m architecture reference manual?.
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 27 - revision v2.03 5.2.6 nested vectored interrupt controller (nvic) cortex-m0 provides an interrupt c ontroller as an integral part of the exception mode, named as ?nested vectored interrupt controller (nvic)?. it is closely coupled to the processor kernel and provides following features: z nested and vectored interrupt support z automatic processor stat e saving and restoration z reduced and deterministic interrupt latency the nvic prioritizes and handles all supported ex ceptions. all exceptions are handled in ?handler mode?. this nvic architecture su pports 32 (irq[31:0]) discrete interrupts with 4 levels of priority. all of the interrupts and most of the system exceptions can be configured to different priority levels. when an interrupt occurs, the nvic will com pare the priority of t he new interrupt to the current running one?s priority. if the priority of t he new interrupt is higher than the current one, the new interrupt handler will override the current handler. when any interrupts is accepted, the starting addr ess of the interrupt se rvice routine (isr) is fetched from a vector table in memory. there is no need to determine which interrupt is accepted and branch to the starting address of the correlat ed isr by software. while the starting address is fetched, nvic will also automatically save proc essor state including the registers ?pc, psr, lr, r0~r3, r12? to the stack. at the end of the isr, the nvic will restore the mentioned registers from stack and resume t he normal execution. thus it will ta ke less and deterministic time to process the interrupt request. the nvic supports ?tail chaining? which handles back-to-back interrupts e fficiently without the overhead of states saving and restoration and t herefore reduces delay time in switching to pending isr at the end of current isr. the nvic al so supports ?late arrival? which improves the efficiency of concurrent isrs. when a higher prio rity interrupt request oc curs before the current isr starts to execute (at the stage of state saving and starting address fetching), the nvic will give priority to the higher one without delay penal ty. thus it advances the real-time capability. for more detailed information, please refer to the documents ?arm ? cortex?-m0 technical reference manual? and ?arm ? v6-m architecture reference manual?.
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 28 - revision v2.03 5.2.6.1 exception model and system interrupt map table 5-2 lists the exception model supported by numicro ? nuc100 series. software can set four levels of priority on some of these exceptio ns as well as on all interrupts. the highest user- configurable priority is denoted as ?0? and the lowest priority is denoted as ?3?. the default priority of all the user-configurable interrupts is ?0?. note t hat priority ?0? is treated as the fourth priority on the system, after three system except ions ?reset?, ?nmi? and ?hard fault?. exception name vector number priority reset 1 -3 nmi 2 -2 hard fault 3 -1 reserved 4 ~ 10 reserved svcall 11 configurable reserved 12 ~ 13 reserved pendsv 14 configurable systick 15 configurable interrupt (irq0 ~ irq31) 16 ~ 47 configurable table 5-2 exception model vector number interrupt number (bit in interrupt registers) interrupt name source ip interrupt description 0 ~ 15 - - - system exceptions 16 0 bod_out brown-out brown-out low voltage detected interrupt 17 1 wdt_int wdt watchdog timer interrupt 18 2 eint0 gpio external signal interrupt from pb.14 pin 19 3 eint1 gpio external signal interrupt from pb.15 pin 20 4 gpab_int gpio external signal interr upt from pa[15:0]/pb[13:0] 21 5 gpcde_int gpio external interrupt from pc[15:0]/pd[15:0]/pe[15:0] 22 6 pwma_int pwm0~3 pwm0, pwm1, pwm2 and pwm3 interrupt 23 7 pwmb_int pwm4~7 pwm4, pwm5, pwm6 and pwm7 interrupt 24 8 tmr0_int tmr0 timer 0 interrupt 25 9 tmr1_int tmr1 timer 1 interrupt
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 29 - revision v2.03 vector number interrupt number (bit in interrupt registers) interrupt name source ip interrupt description 26 10 tmr2_int tmr2 timer 2 interrupt 27 11 tmr3_int tmr3 timer 3 interrupt 28 12 uart02_int uart0/2 uart0 and uart2 interrupt 29 13 uart1_int uart1 uart1 interrupt 30 14 spi0_int spi0 spi0 interrupt 31 15 spi1_int spi1 spi1 interrupt 32 16 spi2_int spi2 spi2 interrupt 33 17 spi3_int spi3 spi3 interrupt 34 18 i2c0_int i 2 c0 i 2 c0 interrupt 35 19 i2c1_int i 2 c1 i 2 c1 interrupt 36 20 reserved reserved reserved 37 21 reserved reserved reserved 38 22 reserved reserved reserved 39 23 usb_int usbd usb 2.0 fs device interrupt 40 24 ps2_int ps/2 ps/2 interrupt 41 25 acmp_int acmp analog comparator-0 or comaprator-1 interrupt 42 26 pdma_int pdma pdma interrupt 43 27 i2s_int i 2 s i 2 s interrupt 44 28 pwrwu_int clkc clock controller interrupt for chip wake-up from power down state 45 29 adc_int adc adc interrupt 46 30 reserved reserved reserved 47 31 rtc_int rtc real time clock interrupt table 5-3 system interrupt map
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 30 - revision v2.03 5.2.6.2 vector table when any interrupts is accepted, the processor will automatically fetch the starting address of the interrupt service routine (isr) from a vector table in memory. for armv6-m, the vector table base address is fixed at 0x00000000. t he vector table contains the initialization value for the stack pointer on reset, and the entry point addresses for all exception handlers. the vector number on previous page defines the order of entries in t he vector table associated with exception handler entry as illustrated in previous section. vector table word offset description 0 sp_main ? the main stack pointer vector number exception entry po inter using that vector number table 5-4 vector table format 5.2.6.3 operation description nvic interrupts can be enabled and disabled by writing to their corresponding interrupt set- enable or interrupt clear-enable r egister bit-field. the registers use a write-1-to-enable and write- 1-to-clear policy, both registers reading back the current enabled stat e of the corresponding interrupts. when an interrupt is disabled, interr upt assertion will cause the interrupt to become pending, however, the interrupt will not activate. if an interrupt is active when it is disabled, it remains in its active state until cleared by rese t or an exception return. clearing the enable bit prevents new activations of the associated interrupt. nvic interrupts can be pended/un-pended using a complementary pair of registers to those used to enable/disable the interrupts, named the se t-pending register and clear-pending register respectively. the registers use a write-1-to-en able and write-1-to-clear policy, both registers reading back the current pended state of the corresponding interrupts. the clear-pending register has no effect on the execut ion status of an active interrupt. nvic interrupts are prioritized by updating an 8-bi t field within a 32-bit register (each register supporting four interrupts). the general registers associated with the nvic are all accessibl e from a block of memory in the system control space and will be described in next section.
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 31 - revision v2.03 5.3 clock controller 5.3.1 overview the clock controller generates the clocks for the whole chip, including system clocks and all peripheral clocks. the clock controller also im plements the power control function with the individually clock on/off control, clock source se lection and a clock divider. the chip will not enter power down mode until cpu sets the power down enable bit (pwr_down_en) and cortex-m0 core executes the wfi instruction. after that, chip ent er power down mode and wait for wake-up interrupt source triggered to leave power down mode. in the power down mode, the clock controller turns off the external 4~24 mhz high speed crystal and internal 22.1184 mhz high speed oscillator to reduce the ov erall system power consumption.
numicro? nuc100 data sheet 1 0 pllcon[19] 22.1184 mhz 4~12 mhz pllfout 111 011 010 001 4~24 mhz 32.768 khz 4~24 mhz hclk 22.1184 mhz 000 1/2 1/2 1/2 clksel0[5:3] 1 0 systick tmr 3 adc uart 0-2 pdma acmp i2c 0~1 spi 0-3 usb i2s rtc ps2 fdiv pwm 0-1 wdt pwm 2-3 pwm 4-5 pwm 6-7 tmr 0 tmr 1 tmr 2 cpu fmc ebi 32.768 khz 10 khz 111 010 001 000 hclk 32.768 khz 4~24 mhz 111 011 010 001 pllfout 32.768 khz 4~24 mhz 10 khz 22.1184 mhz 000 clksel0[2:0] syst_csr[2] cpuclk 1/(hclk_n+1) pclk cpuclk hclk 11 01 00 pllfout 4~24 mhz 22.1184 mhz clksel1[3:2] clksel1[25:24] 22.1184 mhz clksel1[22:20] clksel1[18:16] clksel1[14:12] clksel1[10:8] 1/(usb_n+1) pllfout 11 10 01 00 hclk pllfout 4~24 mhz 22.1184 mhz 11 10 01 00 hclk 4~24 mhz 22.1184 mhz 32.768 khz clksel2[7:2] clksel1[31:28] 22.1184 mhz 32.768 khz bod 10 khz 1/(adc_n+1) clksel2[1:0] 11 10 clksel1[1:0] hclk 1/2048 1/(uart_n+1) 22.1184 mhz 4~24 mhz figure 5-3 clock generator global view diagram publication release date: jan. 2, 2012 - 32 - revision v2.03
numicro? nuc100 data sheet 5.3.2 clock generator the clock generator consists of 5 clock sources which are listed below: z one external 32.768 khz low speed crystal z one external 4~24 mhz high speed crystal z one programmable pll fout(pll source cons ists of external 4~24 mhz high speed crystal and internal 22.1184 mhz high speed oscillator) z one internal 22.1184 mhz high speed oscillator z one internal 10 khz low speed oscillator xt_out external 4~24 mhz crystal xtl12m_en (pwrcon[0]) xt_in internal 22.1184 mhz oscillator osc22m_en (pwrcon[2]) 0 1 pll pll_src (pllcon[19]) pll fout x32o external 32.768 khz crystal 32.768 khz xtl32k_en (pwrcon[1]) x32i internal 10 khz oscillator osc10k_en(pwrcon[3]) 4~24 mhz 22.1184 mhz 10 khz figure 5-4 clock generator block diagram publication release date: jan. 2, 2012 - 33 - revision v2.03
numicro? nuc100 data sheet 5.3.3 system clock and systick clock the system clock has 5 clock sources which we re generated from clock generator block. the clock source switch depends on the register hclk_s (clksel0[2:0]). the block diagram is showed in figure 5-5 . 111 011 010 001 pllfout 32.768 khz 4~24 mhz 10 khz hclk_s (clksel0[2:0]) 22.1184 mhz 000 1/(hclk_n+1) hclk_n (clkdiv[3:0]) cpu in power down mode cpu ahb apb cpuclk hclk pclk figure 5-5 system clock block diagram the clock source of sy pu clock or external clock stick in cortex-m0 core can use c (syst_csr[2]). if using external clock, the sy stick clock (stclk) has 5 clock sources. the clock source switch depends on the setting of the register stclk_s (c lksel0[5:3]). the block diagram is showed in figure 5-6 . figure 5-6 systick clock control block diagram publication release date: jan. 2, 2012 - 34 - revision v2.03
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 35 - revision v2.03 5.3.4 peripherals clock the peripherals clock had different clock source switch setting which depends on the different peripheral. please refer the clksel1 and cl ksel2 register description in 5.3.7. 5.3.5 power down mode clock when chip enters into power down mode, syst em clocks, some clock sources, and some peripheral clocks will be di sabled. some cloc k sources and peripherals clock are still active in power down mode. for theses clocks which still keep active list below: z clock generator ? internal 10 khz low speed oscillator clock ? external 32.768 khz low speed crystal clock z peripherals clock (when wdt adopt internal 10 khz low speed oscillator as clock source and rtc adopt external 32.768 kh z low speed crystal as clock source)
numicro? nuc100 data sheet 5.3.6 frequency divider output this device is equipped a power-of-2 frequency divider which is composed by16 chained divide- by-2 shift registers. one of the 16 shift register outputs selected by a sixteen to one multiplexer is reflected to clko function pin. therefore there are 16 options of power-of-2 divided clocks with the frequency from f in /2 1 to f in /2 16 where fin is input clock frequency to the clock divider. the output formula is f out = f in /2 (n+1) , where f in is the input clock frequency, f out is the clock divider output frequency and n is the 4-bit value in fsel (frqdiv[3:0]). when write 1 to divider_en (frq div[4]), the chained counter starts to count. when write 0 to divider_en (frqdiv[4]), the c hained counter continuously runs till divided clock reaches low state and stay in low state. figure 5-7 clock source of frequency divider figure 5-8 block diagram of frequency divider publication release date: jan. 2, 2012 - 36 - revision v2.03
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 37 - revision v2.03 5.4 general purpose i/o (gpio) 5.4.1 overview numicro ? nuc100/nuc120 medium density has up to 80 general purpose i/o pins can be shared with other function pins; it depends on the chip configuration. these 80 pins are arranged in 5 ports named with gpioa, gpiob, gpio c, gpiod and gpioe. each port equips maximum 16 pins. each one of the 80 pins is independent and has the corresponding register bits to control the pin mode function and data. numicro ? nuc100/nuc120 low density has up to 65 general purpose i/o pins can be shared with other function pins; it depends on the chip configuration and package. these 65 pins are arranged in 4 ports named with gpioa, gpiob, gpioc and gpiod with each port equips maximum 16 pins and another port named gpioe with 1 pins pe.5. the i/o type of each of i/o pins can be configur ed by software individually as input, output, open- drain or quasi-bidirectional mode. after reset, the i/o type of all pins stay in quasi-bidirectional mode and port data register gpiox_dout[15:0] resets to 0x0000_ffff. each i/o pin equips a very weakly individual pull-up resistor which is about 110k ~300k for v dd is from 5.0 v to 2.5 v. 5.4.2 features z four i/o modes: ? quasi bi-direction ? push-pull output ? open-drain output ? input only with high impendence z ttl/schmitt trigger input selectable z i/o pin can be configured as inte rrupt source with edge/level setting z high driver and high sink io mode support
numicro? nuc100 data sheet 5.5 i 2 c serial interface controller (master/slave) (i 2 c) 5.5.1 overview i 2 c is a two-wire, bi-directional se rial bus that provides a simple and efficient method of data exchange between devices. the i 2 c standard is a true multi-master bus including collision detection and arbitration that prevents data corrupt ion if two or more masters attempt to control the bus simultaneously. data is transferred between a master and a slave synchronously to scl on the sda line on a byte-by-byte basis. each data byte is 8-bit long. there is one scl clock pulse for each data bit with the msb being transmitted first. an acknowledge bit follows each transferred byte. each bit is sampled during the high period of scl; therefore, the sda line may be changed only during the low period of scl and must be held stable during the high period of scl. a transition on the sda line while scl is high is interpreted as a command (start or stop). please refer to the figure 5-9 for more detail i 2 c bus timing. figure 5-9 i 2 c bus timing the device?s on-chip i 2 c logic provides the serial interface that meets the i 2 c bus standard mode specification. the i 2 c port handles byte transfers autonomousl y. to enable this port, the bit ens1 in i2con should be set to '1'. the i 2 c h/w interfaces to the i 2 c bus via two pins: sda and scl. pull up resistor is needed for i 2 c operation as these are open drain pins. when the i/o pins are used as i 2 c port, user must set the pins function to i 2 c in advance. publication release date: jan. 2, 2012 - 38 - revision v2.03
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 39 - revision v2.03 5.5.2 features the i 2 c bus uses two wires (sda and scl) to transf er information between devices connected to the bus. the main featur es of the bus are: z master/slave mode z bidirectional data transfer between masters and slaves z multi-master bus (no central master) z arbitration between simultaneously transmi tting masters without corruption of serial data on the bus z serial clock synchronization allows devices with different bit rates to communicate via one serial bus z serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer z built-in a 14-bit time-out counter will request the i 2 c interrupt if the i 2 c bus hangs up and timer-out counter overflows. z external pull-up are needed for high output z programmable clocks allow versatile rate control z supports 7-bit addressing mode z i 2 c-bus controllers support multiple address recognition ( four slave address with mask option)
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 40 - revision v2.03 5.6 pwm generator and capture timer (pwm) 5.6.1 overview numicro ? nuc100/nuc120 medium density has 2 sets of pwm group supports total 4 sets of pwm generators which can be configured as 8 independent pwm outputs, pwm0~pwm7, or as 4 complementary pwm pairs, (pwm0, pwm1), (pwm2, pwm3), (pwm4, pwm5) and (pwm6, pwm7) with 4 programmable dead-zone generators. numicro ? nuc100/nuc120 low density only support 1 set of pwm group supports tota l 2 sets of pwm generators which can be configured as 4 independent pwm outputs, pw m0~pwm3, or as 2 complementary pwm pairs, (pwm0, pwm1) and (pwm2, pwm3) with 2 programmable dead-zone generators. each pwm generator has one 8-bit prescaler, one clock divider with 5 divided frequencies (1, 1/2, 1/4, 1/8, 1/16), two pwm timers including two clock selectors, two 16-bit pwm down- counters for pwm period control, two 16-bit comparators for pwm duty control and one dead- zone generator. the 4 sets of pwm generator s provide eight independent pwm interrupt flags which are set by hardware when the corresponding pwm period down counter reaches zero. each pwm interrupt source with its corresponding enable bit can cause cpu to request pwm interrupt. the pwm generators can be configured as one-shot mode to produce only one pwm cycle signal or auto-reload mode to output pwm waveform continuously. when pcr.dzen01 is set, pwm0 and pwm1 perf orm complementary pwm paired function; the paired pwm period, duty and dead-time are determined by pwm0 timer and dead-zone generator 0. similarly, the complementary pw m pairs of (pwm2, pwm3), (pwm4, pwm5) and (pwm6, pwm7) are controlled by pwm2, pwm4 and pwm6 timers and dead-zone generator 2, 4 and 6, respectively. to prevent pwm driving output pin with unsteady waveform, the 16-bit period down counter and 16-bit comparator are implemented with double buffer. when user writes data to counter/comparator buffer registers the updated value will be load into the 16-bit down counter/ comparator at the time down counter reaching ze ro. the double buffering feature avoids glitch at pwm outputs. when the 16-bit period down counter reaches ze ro, the interrupt request is generated. if pwm- timer is set as auto-reload mode, when the down counter reaches zero, it is reloaded with pwm counter register (cnrx) automatically then start decreasing, repeatedly. if the pwm-timer is set as one-shot mode, the down count er will stop and generate one interrupt request when it reaches zero. the value of pwm counter comparator is used for pulse high width modulation. the counter control logic changes the output to high level when down-counter value matches the value of compare register. the alternate feature of the pwm-timer is digita l input capture function. if capture function is enabled the pwm output pin is switched as capture input mode. the capture0 and pwm0 share one timer which is included in pwm0 and the c apture1 and pwm1 share pwm1 timer, and etc. therefore user must setup the pwm-timer before ena ble capture feature. a fter capture feature is enabled, the capture always latched pwm-counter to capture rising latch register (crlr) when input channel has a rising transition and latched pwm-counter to capture falling latch register (cflr) when input channel has a fallin g transition. capture channel 0 interrupt is programmable by setting ccr0.crl_ie0[1 ] (rising latch interrupt enable) and ccr0.cfl_ie0[2]] (falling latch interrupt enable) to decide the condition of interrupt occur. capture channel 1 has the same feature by setting ccr0.crl_ie1[17] and ccr0.cfl_ie1[18]. and capture channel 2 to channel 3 on each group have the same feature by setting the corresponding control bits in ccr2. for each grou p, whenever capture issu es interrupt 0/1/2/3,
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 41 - revision v2.03 the pwm counter 0/1/2/3 will be reload at this moment. the maximum captured frequency that pwm can c apture is confined by the capture interrupt latency. when capture interrupt occurred, software will do at l east three steps, they are: read piir to get interrupt source and read crlrx/cflr x(x=0~3) to get capture value and finally write 1 to clear piir to zero. if interrupt latency will ta ke time t0 to finish, the capture signal mustn?t transition during this interval (t0). in this ca se, the maximum capture frequency will be 1/t0. for example: hclk = 50 mhz, pwm_clk = 25 mhz, interrupt latency is 900 ns so the maximum capture frequency will is 1/900ns 1000 khz 5.6.2 features 5.6.2.1 pwm function features: z pwm group has two pwm generators. each pwm generator supports one 8-bit prescaler, one clock divider, two pwm-timers (down counter), one dead-zone generator and two pwm outputs. z up to 16-bit resolution z pwm interrupt request synchronized with pwm period z one-shot or auto-reload mode pwm z up to 2 pwm group (pwma/pwmb) to support 8 pwm channels or 4 pwm paired channels (only 1 pwm group support for numicro ? nuc100/nuc120 low density) 5.6.2.2 capture function features: z timing control logic shar ed with pwm generators z support 8 capture input channels shar ed with 8 pwm output channels (numicro ? nuc100/nuc120 low density only support 4 capture input channels shared with 4 pwm output channels) z each channel supports one rising latch r egister (crlr), one falling latch register (cflr) and capture interrupt flag (capifx)
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 42 - revision v2.03 5.7 real time clock (rtc) 5.7.1 overview real time clock (rtc) controller provides user the real time and calendar message. the clock source of rtc is from an external 32.768 khz low speed crystal connected at pins x32i and x32o (reference to pin descript ions) or from an external 32.768 khz low speed oscillator output fed at pin x32i. the rtc controller provides the time message (second, minute, hour) in time loading register (tlr) as well as calendar mess age (day, month, year) in calendar loading register (clr). the data message is expressed in bcd format. it also offers alarm function that user can preset the alarm time in time alar m register (tar) and alarm calendar in calendar alarm register (car). the rtc controller supports periodic time tick and alarm match interrupts. the periodic interrupt has 8 period options 1/128, 1/64, 1/32, 1/16, 1/ 8, 1/4, 1/2 and 1 second which are selected by ttr (ttr[2:0]). when rtc counter in tlr and clr is equal to alarm setting time registers tar and car, the alarm interrupt flag (riir.aif) is set and the alarm interrupt is requested if the alarm interrupt is enabled (rier.aier=1). both rtc ti me tick and alarm match can cause chip wake- up from power down mode if wake-up function is enabled (twke (ttr[3])=1). 5.7.2 features z there is a time counter (second, minute, hou r) and calendar counter (day, month, year) for user to check the time z alarm register (second, minut e, hour, day, month, year) z 12-hour or 24-hour mode is selectable z leap year compensation automatically z day of week counter z frequency compensate register (fcr) z all time and calendar message is expressed in bcd code z support periodic time tick interrupt with 8 peri od options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second z support rtc time tick and alarm match interrupt z support wake-up chip from power down mode
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 43 - revision v2.03 5.8 serial peripheral interface (spi) 5.8.1 overview the serial peripheral interface (spi) is a synchronous serial data communication protocol which operates in full duplex mode. devices communicate in master/slave mode with 4-wire bi-direction interface. the numicro ? nuc100/nuc120 medium density contains up to four sets of spi controller performing a serial-to-parallel conver sion on data received from a peripheral device, and a parallel-to-serial conversion on data transmit ted to a peripheral device. each set of spi controller can be set as a master that can drive up to 2 external peripheral slave devices; it also can be configured as a slave device contro lled by an off-chip master device. numicro ? nuc100/nuc120 low density contains two sets of spi controller only. this controller supports a variable serial clock for special application and it also supports 2-bit transfer mode to connect 2 off-chip slave devic es at the same time. the spi controller also supports pdma function to access the data buffer. 5.8.2 features z up to four sets of spi controller for numicro ? nuc100/nuc120 medium density z up to two sets of spi controller for numicro ? nuc100/nuc120 low density z support master or slave mode operation z support 1-bit or 2-bit transfer mode z configurable bit length up to 32-bit of a tran sfer word and configurable word numbers up to 2 of a transaction, so the maximum bit l ength is 64-bit for each data transfer z provide burst mode operation, transmit/receive can be transferred up to two times word transaction in one transfer z support msb or lsb first transfer z 2 device/slave select lines in master mode, but 1 device/slave select line in slave mode z support byte reorder function z support byte or word suspend mode z variable output serial clock frequency in master mode z support two programmable serial clock frequencies in master mode z support two channel pdma request, one for transmitter and another for receiver
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 44 - revision v2.03 5.9 timer controller (tmr) 5.9.1 overview the timer controller includes four 32-bit timers , timer0~timer3, which allows user to easily implement a timer control for applications. the timer can perform functions like frequency measurement, event counting, inte rval measurement, clock generati on, delay timing, and so on. the timer can generates an interrupt signal upon timeout, or provide the current value during operation. note: toggle mode, continuous coun ting mode and event counting function only support in numicro ? nuc100/nuc120 low density. 5.9.2 features z 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit pre-scale counter z independent clock source for each timer z provides one-shot, periodic, toggle and continuous counting operation modes (numicro ? nuc100/nuc120 medium density only support one-shot and periodic mode) z time out period = (period of timer clock input) * (8-bit pre-scale counter + 1) * (24-bit tcmp) z maximum counting cycle time = (1 / t mhz) * (2 8 ) * (2 24 ), t is the period of timer clock z 24-bit timer value is readable through tdr (timer data register) z support event counting function to count the event from external pin ( numicro ? nuc100/nuc120 low density only )
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 45 - revision v2.03 5.10 watchdog timer (wdt) 5.10.1 overview the purpose of watchdog timer is to perform a sy stem reset when system runs into an unknown state. this prevents sy stem from hanging for an infinite period of time. besides, this watchdog timer supports another function to wake-up chip from power down mode. the watchdog timer includes an 18-bit free running counter with programmable time-out intervals. table 5-5 show the watchdog timeout interval selection and figure 5- 64 shows the timing of watchdog interrupt signal and reset signal. setting wte (wdtcr [7]) enables the watchdog ti mer and the wdt counter starts counting up. when the counter reaches the selected time-out interval, watchdog timer interrupt flag wtif will be set immediately to request a wdt interrupt if the watchdog timer interrupt enable bit wtie is set, in the meanwhile, a specified delay time (1024 * t wdt ) follows the time-out event. user must set wtr (wdtcr [0]) (watchdog timer reset) high to reset the 18-bit wdt counter to avoid chip from watchdog timer reset before the delay time expires. wtr bit is cl eared automatically by hardware after wdt counter is reset. there are eight time-out intervals with specific delay time which are selected by watchdog timer interval select bits wtis (wdt cr [10:8]). if the wdt counter has not been cleared after the specific delay time expires, t he watchdog timer will set watchdog timer reset flag (wtrf) high and reset chip. this reset will last 63 wdt clocks (t rst ) then chip restarts executing pr ogram from reset vector (0x0000_0000). wtrf will not be cleared by watchdog reset. user may poll wtrf by software to recognize the reset source. wdt also provides wake-up function. when chip is powered down and the watchdog timer wake-up function enable bit (wdtr[4]) is set, if the wd t counter reaches the specific time interval defined by wtis (wdtcr [10:8]) , the chip is wake n up from power down state. first example, if wtis is set as 000, the specific time interval for chip to wake up from power down state is 2 4 * t wdt . when power down command is set by software, then, chip enters power down state. after 2 4 * t wdt time is elapsed, chip is waken up from power down state. second example, if wtis (wdtcr [10:8]) is set as 111, the specific time interval for chip to wake up from power down state is 2 18 * t wdt . if power down command is set by software, then, chip enters power down state. after 2 18 * t wdt time is elapsed, chip is waken up from power down state. notice if wtre (wdtcr [1]) is set to 1, after chip is wake n up, software should clear the watchdog timer counter by setting wtr(wdtcr [0]) to 1 as soon as possible. otherwise, if the watchdog timer counter is not cleared by setting wtr (wdtcr [0]) to 1 before time starting from waking up to software clearing watchdog timer counter is over 1024 * t wdt , the chip is reset by watchdog timer. wtis timeout interval selection t tis interrupt period t int wtr timeout interval (wdt_clk=10 khz) min. t wtr ~ max. t wtr 000 2 4 * t wdt 1024 * t wdt 1.6 ms ~ 104 ms 001 2 6 * t wdt 1024 * t wdt 6.4 ms ~ 108.8 ms 010 2 8 * t wdt 1024 * t wdt 25.6 ms ~ 128 ms 011 2 10 * t wdt 1024 * t wdt 102.4 ms ~ 204.8 ms 100 2 12 * t wdt 1024 * t wdt 409.6 ms ~ 512 ms 101 2 14 * t wdt 1024 * t wdt 1.6384 s ~ 1.7408 s 110 2 16 * t wdt 1024 * t wdt 6.5536 s ~ 6.656 s 111 2 18 * t wdt 1024 * t wdt 26.2144 s ~ 26.3168 s table 5-5 watchdog timeout interval selection
numicro? nuc100 data sheet t tis rst int 1024 * t wdt 63 * t wdt minimum t wtr t int t rst maximum t wtr t wdt t wdt : watchdog engine clock time period t tis : watchdog timeout interval selection period t int : watchdog interrupt period t rst : watchdog reset period t wtr : watchdog timeout interval period figure 5-10 timing of interrupt and reset signal publication release date: jan. 2, 2012 - 46 - revision v2.03
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 47 - revision v2.03 5.10.2 features z 18-bit free running counter to avoid chip fr om watchdog timer reset before the delay time expires. z selectable time-out interval (2 4 ~ 2 18 ) and the time out interval is 104 ms ~ 26.3168 s (if wdt_clk = 10 khz). z reset period = (1 / 10 khz) * 63, if wdt_clk = 10 khz. 5.11 uart interface controller (uart) numicro ? nuc100/nuc120 medium density provides up to three channels of universal asynchronous receiver/transmitters (uart). uart0 supports high speed uart and uart1~2 perform normal speed uart, besides, only uart 0 and uart1 support flow control function. numicro ? nuc100/nuc120 low density only supports uart0 and uart1. 5.11.1 overview the universal asynchronous receiver/transmitter (uart) performs a serial-to-parallel conversion on data received from the periphera l, and a parallel-to-serial conversion on data transmitted from the cpu. the uart controller also supports irda sir function and rs-485 mode functions. each uart channel supports seven types of interrupts including transmitter fifo empty interrupt (int_thre), receiver thre shold level reaching interrupt (int_rda), line status interrupt (parity error or framing error or break interrupt) (int_rls), receiver buffer time out interrupt (int_tout), modem/wake-up status in terrupt (int_modem) and buffer error interrupt (int_buf_err). interrupts of uart0 and uart2 share the interrupt number 12 (vector number is 28); interrupt number 13 (vector number is 29) only supports uart1 interrupt. refer to nested vectored interrupt controller chapt er for system interrupt map. the uart0 is built-in with a 64-byte transmitter fifo (tx_fifo) and a 64-byte receiver fifo (rx_fifo) that reduces the number of interrupts presented to the cpu and the uart1~2 are equipped 16-byte transmitter fifo (tx_fifo) and 16 -byte receiver fifo (rx_fifo). the cpu can read the status of the uart at any time during the operation. the reported status information includes the type and condition of the transfer operations being pe rformed by the uart, as well as 4 error conditions (parity error, framing error, break interrupt and buffer error) probably occur while receiving data. the uart includes a prog rammable baud rate generator that is capable of dividing clock input by divisors to produce the seri al clock that transmitter and receiver need. the baud rate equation is baud rate = uart_clk / m * [brd + 2], where m and brd are defined in baud rate divider register (ua_baud). table 5-6 lists the equations in the various conditions and table 5-7 list the uart baud rate setting table. mode div_x_en div_x_one divider x brd baud rate equation 0 0 0 b a uart_clk / [16 * (a+2)] 1 1 0 b a uart_clk / [(b+1) * (a+2)] , b must >= 8 2 1 1 don?t care a uart_clk / (a+2), a must >=3 table 5-6 uart baud rate equation
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 48 - revision v2.03 system clock = internal 22.1184 mhz high speed oscillator mode0 mode1 mode2 baud rate parameter register parameter register parameter register 921600 x x a=0,b=11 0x2b00_0000 a=22 0x3000_0016 460800 a=1 0x0000_0001 a=1,b=15 a=2,b=11 0x2f00_0001 0x2b00_0002 a=46 0x3000_002e 230400 a=4 0x0000_0004 a=4,b=15 a=6,b=11 0x2f00_0004 0x2b00_0006 a=94 0x3000_005e 115200 a=10 0x0000_000a a=10,b=15 a=14,b=11 0x2f00_000a 0x2b00_000e a=190 0x3000_00be 57600 a=22 0x0000_0016 a=22,b=15 a=30,b=11 0x2f00_0016 0x2b00_001e a=382 0x3000_017e 38400 a=34 0x0000_0022 a=62,b=8 a=46,b=11 a=34,b=15 0x2800_003e 0x2b00_002e 0x2f00_0022 a=574 0x3000_023e 19200 a=70 0x0000_0046 a=126,b=8 a=94,b=11 a=70,b=15 0x2800_007e 0x2b00_005e 0x2f00_0046 a=1150 0x3000_047e 9600 a=142 0x0000_008e a=254,b=8 a=190,b=11 a=142,b=15 0x2800_00fe 0x2b00_00be 0x2f00_008e a=2302 0x3000_08fe 4800 a=286 0x0000_011e a=510,b=8 a=382,b=11 a=286,b=15 0x2800_01fe 0x2b00_017e 0x2f00_011e a=4606 0x3000_11fe table 5-7 uart baud rate setting table the uart0 and uart1 controllers support auto-flow control function that uses two low-level signals, /cts (clear-to-send) and /rts (request- to-send), to control the flow of data transfer between the uart and external devices (ex: mode m). when auto-flow is enabled, the uart is not allowed to receive data until the uart assert s /rts to external dev ice. when the number of bytes in the rx fifo equals the value of rt s_tri_lev (ua_fcr [19:16]), the /rts is de- asserted. the uart sends data out when uart cont roller detects /cts is asserted from external device. if a valid asserted /cts is not detected the uart controller will not send data out. the uart controllers also provides serial irda (sir, serial infrared) function (user must set irda_en (ua_fun_sel [1]) to enable irda function ). the sir specificatio n defines a short-range infrared asynchronous serial transmission mode wi th one start bit, 8 data bits, and 1 stop bit. the maximum data rate is 115.2 kbps (half duplex ). the irda sir block contains an irda sir protocol encoder/decoder. the irda sir protocol is half-duplex onl y. so it cannot transmit and receive data at the same time. the irda sir phy sical layer specifies a minimum 10ms transfer delay between transmission and reception. this del ay feature must be implemented by software. for numicro ? nuc100/nuc120 low density, another alter nate function of uart controllers is rs-485 9-bit mode function, and direction control provided by rts pin or can program gpio (pb.2 for rts0 and pb.6 for rts1) to implement the function by software. the rs-485 mode is selected by setting the ua_fun_sel register to select rs-485 function. the rs-485 driver control is implemented using the rts control signal from an asynchronous serial port to enable the rs-485 driver. in rs-485 mode, many characteristics of the rx and tx are same as uart.
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 49 - revision v2.03 5.11.2 features z full duplex, asynchronous communications z separate receive / transmit 64/16/16 bytes (u art0/uart1/uart2) entry fifo for data payloads z support hardware auto flow control/flow control function (cts, rts) and programmable rts flow control trigger level (uart0 and uart1 support) z programmable receiver buffer trigger level z support programmable baud-rate generator for each channel individually z support cts wake-up function (uart0 and uart1 support) z support 7-bit receiver buffer time out detection function z uart0/uart1 can be served by the dma controller z programmable transmitting data delay time bet ween the last stop and the next start bit by setting ua_tor [dly] register z support break error, frame erro r, parity error and receive / transmit buffer overflow detect function z fully programmable serial-interface characteristics ? programmable number of data bit, 5-, 6-, 7-, 8-bit character ? programmable parity bit, even, odd, no par ity or stick parity bit generation and detection ? programmable stop bit, 1, 1.5, or 2 stop bit generation z support irda sir function mode ? support for 3-/16-bit duration for normal mode z support rs-485 function mode. (numicro ? nuc100/nuc120 low density only) ? support rs-485 9-bit mode ? support hardware or software direct enable control provided by rts pin
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 50 - revision v2.03 5.12 ps/2 device controller (ps2d) 5.12.1 overview ps/2 device controller provides basic timing c ontrol for ps/2 communication. all communication between the device and the host is managed through the clk and data pins. unlike ps/2 keyboard or mouse device controller, the re ceived/transmit code needs to be translated as meaningful code by firmware. the device controll er generates the clk signal after receiving a request to send, but host has ultimate control over communication. data sent from the host to the device is read on the rising edge and data sent from device to t he host is change after rising edge. a 16 bytes fifo is used to reduce cpu inte rvention. s/w can select 1 to 16 bytes for a continuous transmission. 5.12.2 features z host communication inhibit and request to send detection z reception frame error detection z programmable 1 to 16 bytes transmit buffer to reduce cpu intervention z double buffer for data reception z s/w override bus
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 51 - revision v2.03 5.13 i 2 s controller (i 2 s) 5.13.1 overview the i 2 s controller consists of iis protocol to inte rface with external audio codec. two 8 word deep fifo for read path and write path respectively and is capable of handling 8 ~ 32 bit word sizes. dma controller handles the dat a movement between fifo and memory. 5.13.2 features z i 2 s can operate as either master or slave z capable of handling 8-, 16-, 24- and 32-bit word sizes z mono and stereo audio data supported z i 2 s and msb justified data format supported z two 8 word fifo data buffers are provided, one for transmit and one for receive z generates interrupt requests when buffer levels cross a programmable boundary z two dma requests, one for transmit and one for receive
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 52 - revision v2.03 5.14 analog-to-digital converter (adc) 5.14.1 overview numicro ? nuc100 series contains one 12-bit succ essive approximation analog-to-digital converters (sar a/d converter) with 8 i nput channels. the a/d converter supports three operation modes: single, single-cycle scan and c ontinuous scan mode. the a/d converters can be started by software and external stadc pin. 5.14.2 features z analog input voltage range: 0~v ref z 12-bit resolution and 10-bit accuracy is guaranteed z up to 8 single-end analog input channels or 4 differential analog input channels z maximum adc clock frequency is 16 mhz z up to 600k sps conversion rate z three operating modes ? single mode: a/d conversion is performed one time on a specified channel ? single-cycle scan mode: a/d conversion is performed o ne cycle on all specified channels with the sequence from the lo west numbered channel to the highest numbered channel ? continuous scan mode: a/d converter conti nuously performs single-cycle scan mode until software stops a/d conversion z an a/d conversion can be started by ? software write 1 to adst bit ? external pin stadc z conversion results are held in data register s for each channel with valid and overrun indicators z conversion result can be compared with spec ify value and user can select whether to generate an interrupt when conversion result is equal to the compare register setting z channel 7 supports 3 input sources: exter nal analog voltage, internal bandgap voltage, and internal temperature sensor output z support self-calibration to minimize conversion error
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 53 - revision v2.03 5.15 analog comparator (cmp) 5.15.1 overview numicro ? nuc100 series contains two comparators. the comparators can be used in a number of different configurations. the comparator output is a logical one when positive input greater than negative input, otherwise the output is a zero. each comparator can be configured to cause an interrupt when the comparator output value changes. the block diagram is shown in error! reference source not found. . 5.15.2 features z analog input voltage range: 0~5.0 v z hysteresis function supported z two analog comparators with optional internal reference voltage input at negative end z one interrupt vector for both comparators
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 54 - revision v2.03 5.16 pdma controller (pdma) 5.16.1 overview numicro ? nuc100/nuc120 medium density contains a peripheral direct memory access (pdma) controller that transfers data to and from memory or transfer data to and from apb devices. the pdma has nine channels of dma (p eripheral-to-memory or memory-to-peripheral or memory-to-memory). for each pdma channel (pdma ch0~ch8), there is one word buffer as transfer buffer between the peripherals apb devices and memory. software can stop the pdma operation by dis able pdma [pdmacen]. the cpu can recognize the completion of a pdma operation by software polling or when it receives an internal pdma interrupt. the pdma controller can increase source or destination address or fixed them as well. notice: numicro ? nuc100/nuc120 low density only has 1 pdma channel (channel 0). 5.16.2 features z up to nine dma channels. each channel c an support a unidirectional transfer (numicro ? nuc100/nuc120 low density only has 1 pdma channel) z amba ahb master/slave interface compatible, for data transfer and register read/write z support source and destination address increased mode or fixed mode z hardware channel priority. dma channel 0 has the highest priority and channel 8 has the lowest priority
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 55 - revision v2.03 5.17 external bus interface (ebi) 5.17.1 overview the numicro ? nuc100/nuc120 low density lqfp-64 pack age equips an external bus interface (ebi) for external device used. to save the connections between external devi ce and this chip, ebi support address bus and data bus multiplex mode. and, address latch enable (ale) signal supported differentiate the address and data cycle. 5.17.2 features external bus interface has the following functions: z external devices with max. 64k-byte size (8-bit data width)/128k-byte (16-bit data width) supported z variable external bus base clock (mclk) supported z 8-bit or 16-bit data width supported z variable data access time (tacc), address latch enable time (tale) and address hold time (tahd) supported z address bus and data bus multiplex mode supported to save the address pins z configurable idle cycle supported for different access condition: write command finish (w2x), read-to-read (r2r)
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 56 - revision v2.03 6 flash memory controller (fmc) 6.1 overview numicro ? nuc100 series equips with 128/64/32k byte s on chip embedded flash for application program memory (aprom) that can be updated th rough isp procedure. in system programming (isp) function enables user to update program memory when chip is soldered on pcb. after chip power on, cortex-m0 cpu fetches code from aprom or ldrom decided by boot select (cbs) in config0. by the way, numicro ? nuc100 series also provides additional data flash for user, to store some application dependent data before chip power off. for 128k bytes aprom device, the data flash is shared with original 128k program memory and its start address is configurable and defined by user application request in config1. for 64k/32k byte s aprom device, the data flash is fixed at 4k. 6.2 features z run up to 50 mhz with zero wait state for continuous address read access z 128/64/32kb application program memory (aprom) (numicro ? nuc100/nuc120 low density only support up to 64kb size) z 4kb in system programming (isp) loader program memory (ldrom) z configurable or fixed 4kb data flash with 512 bytes page erase unit z programmable data flash star t address for 128k aprom device z in system program (isp) to update on chip flash
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 57 - revision v2.03 7 electrical characteristics 7.1 absolute maximum ratings symbol parameter min max unit dc power supply v dd ? v ss -0.3 +7.0 v input voltage v in v ss -0.3 v dd +0.3 v oscillator frequency 1/t clcl 4 24 mhz operating temperature ta -40 +85 c storage temperature tst -55 +150 c maximum current into v dd - 120 ma maximum current out of v ss 120 ma maximum current sunk by a i/o pin 35 ma maximum current sourced by a i/o pin 35 ma maximum current sunk by total i/o pins 100 ma maximum current sourced by total i/o pins 100 ma note: exposure to conditions beyond thos e listed under absolute maximum ratings may adversely affects the lift and reliability of the device.
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 58 - revision v2.03 7.2 dc electrical characteristics 7.2.1 numicro ? nuc100/nuc120 medium density dc electrical characteristics (v dd -v ss =3.3 v, ta = 25 c, fosc = 50 mhz unless otherwise specified.) specification parameter sym. min. typ. max. unit test conditions operation voltage v dd 2.5 5.5 v v dd =2.5 v ~ 5.5 v up to 50 mhz power ground v ss av ss -0.3 v ldo output voltage v ldo -10% 2.5 +10% v v dd > 2.7 v analog operating voltage av dd 0 v dd v analog reference voltage vref 0 av dd v i dd1 54 ma v dd = 5.5 v@50 mhz, enable all ip and pll, xtal=12 mhz i dd2 31 ma v dd = 5.5 v@ 50 mhz, disable all ip and enable pll, xtal=12 mhz i dd3 51 ma v dd = 3 v@50 mhz, enable all ip and pll, xtal=12 mhz operating current normal run mode @ 50 mhz i dd4 28 ma v dd = 3 v@50 mhz, disable all ip and enable pll, xtal=12 mhz i dd5 22 ma v dd = 5.5 v@12 mhz, enable all ip and disable pll, xtal=12 mhz i dd6 14 ma v dd = 5.5 v@12 mhz, disable all ip and disable pll, xtal=12 mhz operating current normal run mode @ 12 mhz i dd7 20 ma v dd = 3 v@12mhz, enable all ip and disable pll, xtal=12 mhz
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 59 - revision v2.03 specification parameter sym. min. typ. max. unit test conditions i dd8 12 ma v dd = 3 v@12 mhz, disable all ip and disable pll, xtal=12 mhz i dd9 15 ma v dd = 5 v@4 mhz, enable all ip and disable pll, xtal=4 mhz i dd10 11 ma v dd = 5 v@4 mhz, disable all ip and disable pll, xtal=4 mhz i dd11 13 ma v dd = 3 v@4 mhz, enable all ip and disable pll, xtal=4 mhz operating current normal run mode @ 4 mhz i dd12 9 ma v dd = 3 v@4 mhz, disable all ip and disable pll, xtal=4 mhz i idle1 38 ma v dd = 5.5 v@50 mhz, enable all ip and pll, xtal=12 mhz i idle2 15 ma vdd=5.5 v@50 mhz, disable all ip and enable pll, xtal=12 mhz i idle3 35 ma v dd = 3 v@50 mhz, enable all ip and pll, xtal=12 mhz operating current idle mode @ 50 mhz i idle4 13 ma v dd = 3 v@50 mhz, disable all ip and enable pll, xtal=12 mhz i idle5 13 ma v dd = 5.5 v@12 mhz, enable all ip and disable pll, xtal=12 mhz i idle6 5.5 ma v dd = 5.5 v@12 mhz, disable all ip and disable pll, xtal=12 mhz operating current idle mode @ 12 mhz i idle7 12 ma v dd = 3 v@12 mhz, enable all ip and disable pll, xtal=12 mhz
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 60 - revision v2.03 specification parameter sym. min. typ. max. unit test conditions i idle8 4 ma v dd = 3 v@12 mhz, disable all ip and disable pll, xtal=12 mhz i idle9 8.5 ma v dd = 5 v@4 mhz, enable all ip and disable pll, xtal=4 mhz i idle10 3.5 ma v dd = 5 v@4 mhz, disable all ip and disable pll, xtal=4 mhz i idle11 7 ma v dd = 3 v@4 mhz, enable all ip and disable pll, xtal=4 mhz operating current idle mode @ 4 mhz i idle12 2.5 ma v dd = 3 v@4 mhz, disable all ip and disable pll, xtal=4 mhz i pwd1 23 a v dd = 5.5 v, rtc off, no load @ disable bov function i pwd2 18 a v dd = 3.3 v, rtc off, no load @ disable bov function i pwd3 28 a v dd = 5.5 v, rtc run , no load @ disable bov function standby current power down mode i pwd4 22 a v dd = 3.3 v, rtc run , no load @ disable bov function input current pa, pb, pc, pd, pe (quasi-bidirectional mode) i in1 -50 -60 a v dd = 5.5 v, v in = 0 v or v in =v dd input current at /reset [1] i in2 -55 -45 -30 a v dd = 3.3 v, v in = 0.45 v input leakage current pa, pb, pc, pd, pe i lk -2 - +2 a v dd = 5.5 v, 0 numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 61 - revision v2.03 specification parameter sym. min. typ. max. unit test conditions input high voltage pa, pb, pc, pd, pe (schmitt input) v ih2 0.4 v dd - v dd +0.5 v hysteresis voltage of pa~pe (schmitt input) v hy 0.2 v dd v 0 - 0.8 v dd = 4.5 v input low voltage xt1 [*2] v il3 0 - 0.4 v v dd = 3.0 v 3.5 - v dd +0.2 v v dd = 5.5 v input high voltage xt1 [*2] v ih3 2.4 - v dd +0.2 v dd = 3.0 v input low voltage x32i [*2] v il4 0 - 0.4 v input high voltage x32i [*2] v ih4 1.7 2.5 v negative going threshold (schmitt input), /reset v ils -0.5 - 0.3 v dd v positive going threshold (schmitt input), /reset v ihs 0.7 v dd - v dd +0.5 v i sr11 -300 -370 -450 a v dd = 4.5 v, v s = 2.4 v i sr12 -50 -70 -90 a v dd = 2.7 v, v s = 2.2 v source current pa, pb, pc, pd, pe (quasi-bidirectional mode) i sr13 -40 -60 -80 a v dd = 2.5 v, v s = 2.0 v i sr21 -20 -24 -28 ma v dd = 4.5 v, v s = 2.4 v i sr22 -4 -6 -8 ma v dd = 2.7 v, v s = 2.2 v source current pa, pb, pc, pd, pe (push-pull mode) i sr23 -3 -5 -7 ma v dd = 2.5 v, v s = 2.0 v i sk11 10 16 20 ma v dd = 4.5 v, v s = 0.45 v i sk12 7 10 13 ma v dd = 2.7 v, v s = 0.45 v sink current pa, pb, pc, pd, pe (quasi-bidirectional and push-pull mode) i sk13 6 9 12 ma v dd = 2.5 v, v s = 0.45 v brown-out voltage with bov_vl [1:0] =00b v bo2.2 2.1 2.2 2.3 v brown-out voltage with bov_vl [1:0] =01b v bo2.7 2.6 2.7 2.8 v brown-out voltage with bov_vl [1:0] =10b v bo3.8 3.6 3.8 4.0 v brown-out voltage with bov_vl [1:0] =11b v bo4.5 4.3 4.5 4.7 v hysteresis range of bod voltage v bh 30 - 150 mv v dd = 2.5 v~5.5 v
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 62 - revision v2.03 note: 1. /reset pin is a schmitt trigger input. 2. crystal input is a cmos input. 3. pins of pa, pb, pc, pd and pe can source a transition current when they are being externally driven from 1 to 0. in the condition of v dd =5.5 v, 5he transition current reaches its maximum value when v in approximates to 2 v.
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 63 - revision v2.03 7.2.2 numicro ? nuc100/nuc120 low density dc electrical characteristics (v dd -v ss =3.3 v, ta = 25 c, fosc = 50 mhz unless otherwise specified.) specification parameter sym. min. typ. max. unit test conditions operation voltage v dd 2.5 5.5 v v dd =2.5 v ~ 5.5 v up to 50 mhz power ground v ss av ss -0.3 v ldo output voltage v ldo -10% 2.5 +10% v v dd > 2.7 v analog operating voltage av dd 0 v dd v analog reference voltage vref 0 av dd v i dd1 46 ma v dd = 5.5 v@50 mhz, enable all ip and pll, xtal=12 mhz i dd2 30 ma v dd = 5.5 v@50 mhz, disable all ip and enable pll, xtal=12 mhz i dd3 44 ma v dd = 3 v@50 mhz, enable all ip and pll, xtal=12 mhz operating current normal run mode @ 50 mhz i dd4 28 ma v dd = 3 v@50 mhz, disable all ip and enable pll, xtal=12 mhz i dd5 19 ma v dd = 5.5 v@12 mhz, enable all ip and disable pll, xtal=12 mhz i dd6 13 ma v dd = 5.5 v@12 mhz, disable all ip and disable pll, xtal=12 mhz operating current normal run mode @ 12 mhz i dd7 17 ma v dd = 3 v@12 mhz, enable all ip and disable pll, xtal=12 mhz
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 64 - revision v2.03 specification parameter sym. min. typ. max. unit test conditions i dd8 11.5 ma v dd = 3 v@12 mhz, disable all ip and disable pll, xtal=12 mhz i dd9 13.5 ma v dd = 5 v@4 mhz, enable all ip and disable pll, xtal=4 mhz i dd10 10 ma v dd = 5 v@4 mhz, disable all ip and disable pll, xtal=4 mhz i dd11 12 ma v dd = 3 v@4 mhz, enable all ip and disable pll, xtal=4 mhz operating current normal run mode @ 4 mhz i dd12 8 ma v dd = 3 v@4 mhz, disable all ip and disable pll, xtal=4 mhz i idle1 30 ma v dd = 5.5 v@50 mhz, enable all ip and pll, xtal=12 mhz i idle2 13 ma vdd=5.5 v@50 mhz, disable all ip and enable pll, xtal=12 mhz i idle3 28 ma v dd = 3 v@50 mhz, enable all ip and pll, xtal=12 mhz operating current idle mode @ 50 mhz i idle4 12 ma v dd = 3 v@50 mhz, disable all ip and enable pll, xtal=12 mhz i idle5 11 ma v dd = 5.5 v@12 mhz, enable all ip and disable pll, xtal=12 mhz i idle6 5 ma v dd = 5.5 v@12 mhz, disable all ip and disable pll, xtal=12 mhz operating current idle mode @ 12 mhz i idle7 10 ma v dd = 3 v@12 mhz, enable all ip and disable pll, xtal=12 mhz
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 65 - revision v2.03 specification parameter sym. min. typ. max. unit test conditions i idle8 4 ma v dd = 3 v@12 mhz, disable all ip and disable pll, xtal=12 mhz i idle9 7 ma v dd = 5 v@4 mhz, enable all ip and disable pll, xtal=4 mhz i idle10 3.5 ma v dd = 5 v@4 mhz, disable all ip and disable pll, xtal=4 mhz i idle11 6 ma v dd = 3 v@4 mhz, enable all ip and disable pll, xtal=4 mhz operating current idle mode @ 4 mhz i idle12 2.5 ma v dd = 3 v@4 mhz, disable all ip and disable pll, xtal=4 mhz i pwd1 17 a v dd = 5.5 v, rtc off, no load @ disable bov function i pwd2 14.5 a v dd = 3.3 v, rtc off, no load @ disable bov function i pwd3 20 a v dd = 5.5 v, rtc run , no load @ disable bov function standby current power down mode i pwd4 17 a v dd = 3.3 v, rtc run , no load @ disable bov function input current pa, pb, pc, pd, pe (quasi-bidirectional mode) i in1 -50 -60 a v dd = 5.5 v, v in = 0 v or v in =v dd input current at /reset [1] i in2 -55 -45 -30 a v dd = 3.3 v, v in = 0.45 v input leakage current pa, pb, pc, pd, pe i lk -2 - +2 a v dd = 5.5 v, 0 numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 66 - revision v2.03 specification parameter sym. min. typ. max. unit test conditions input high voltage pa, pb, pc, pd, pe (schmitt input) v ih2 0.4 v dd - v dd +0.5 v hysteresis voltage of pa~pe (schmitt input) v hy 0.2 v dd v 0 - 0.8 v dd = 4.5 v input low voltage xt1 [*2] v il3 0 - 0.4 v v dd = 3.0 v 3.5 - v dd +0.2 v v dd = 5.5 v input high voltage xt1 [*2] v ih3 2.4 - v dd +0.2 v dd = 3.0 v input low voltage x32i [*2] v il4 0 - 0.4 v input high voltage x32i [*2] v ih4 1.7 2.5 v negative going threshold (schmitt input), /reset v ils -0.5 - 0.3 v dd v positive going threshold (schmitt input), /reset v ihs 0.7 v dd - v dd +0.5 v i sr11 -300 -370 -450 a v dd = 4.5 v, v s = 2.4 v i sr12 -50 -70 -90 a v dd = 2.7 v, v s = 2.2 v source current pa, pb, pc, pd, pe (quasi-bidirectional mode) i sr12 -40 -60 -80 a v dd = 2.5 v, v s = 2.0 v i sr21 -20 -24 -28 ma v dd = 4.5 v, v s = 2.4 v i sr22 -4 -6 -8 ma v dd = 2.7 v, v s = 2.2 v source current pa, pb, pc, pd, pe (push-pull mode) i sr22 -3 -5 -7 ma v dd = 2.5 v, v s = 2.0 v i sk1 10 16 20 ma v dd = 4.5 v, v s = 0.45 v i sk1 7 10 13 ma v dd = 2.7 v, v s = 0.45 v sink current pa, pb, pc, pd, pe (quasi-bidirectional and push-pull mode) i sk1 6 9 12 ma v dd = 2.5 v, v s = 0.45 v brown-out voltage with bov_vl [1:0] =00b v bo2.2 2.1 2.2 2.3 v brown-out voltage with bov_vl [1:0] =01b v bo2.7 2.6 2.7 2.8 v brown-out voltage with bov_vl [1:0] =10b v bo3.8 3.6 3.8 4.0 v brown-out voltage with bov_vl [1:0] =11b v bo4.5 4.3 4.5 4.7 v hysteresis range of bod voltage v bh 30 - 150 mv v dd = 2.5 v~5.5 v
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 67 - revision v2.03 specification parameter sym. min. typ. max. unit test conditions bandgap voltage v bg 1.20 1.26 1.32 v v dd = 2.5 v~5.5 v note: 1. /reset pin is a schmitt trigger input. 2. crystal input is a cmos input. 3. pins of pa, pb, pc, pd and pe can source a transition current when they are being externally driven from 1 to 0. in the condition of v dd =5.5 v, 5he transition current reaches its maximum value when v in approximates to 2 v.
numicro? nuc100 data sheet 7.2.3 operating current curve (test condition: run nop) 1. xtal clock = 12 mhz, pll disable, all-ip disable: unit: ma 2. xtal clock = 12 mhz, pll disable, all-ip enable unit: ma publication release date: jan. 2, 2012 - 68 - revision v2.03
numicro? nuc100 data sheet 3. xtal clock = 12 mhz, pll enable, all-ip disable unit: ma 4. xtal clock = 12 mhz, pll enable, all-ip enable unit: ma publication release date: jan. 2, 2012 - 69 - revision v2.03
numicro? nuc100 data sheet 7.2.4 idle current curve 1. xtal clock = 12 mhz, pll disable, all-ip disable unit: ma 2. xtal clock = 12 mhz, pll disable, all-ip enable unit: ma publication release date: jan. 2, 2012 - 70 - revision v2.03
numicro? nuc100 data sheet 3. xtal clock = 12 mhz, pll enable, all-ip disable unit: ma 4. xtal clock = 12 mhz, pll enable, all-ip enable unit: ma publication release date: jan. 2, 2012 - 71 - revision v2.03
numicro? nuc100 data sheet 7.2.5 power down current curve xtal clock = 12 mhz, pll disable unit: ma publication release date: jan. 2, 2012 - 72 - revision v2.03
numicro? nuc100 data sheet 7.3 ac electrical characteristics t clcl t clcx t chcx t clch t chcl note: duty cycle is 50%. symbol parameter condition min. typ. max. unit t chcx clock high time 20 - - ns t clcx clock low time 20 - - ns t clch clock rise time - - 10 ns t chcl clock fall time - - 10 ns 7.3.1 external 4~24 mhz high speed crystal parameter condition min. typ. max. unit input clock frequency external crystal 4 12 24 mhz temperature - -40 - 85 v dd - 2.5 5 5.5 v operating current 12 mhz@ v dd = 5v - 1 - ma 7.3.1.1 typical crystal application circuits crystal c1 c2 r 4 mhz ~ 24 mhz without without without publication release date: jan. 2, 2012 - 73 - revision v2.03
numicro? nuc100 data sheet figure 7-1 typical crystal application circuit 7.3.2 external 32.768 khz low speed crystal parameter condition min. typ. max. unit input clock frequency external crystal - 32.768 - khz temperature - -40 - 85 v dd - 2.5 - 5.5 v 7.3.3 internal 22.1184 mhz high speed oscillator parameter condition min. typ. max. unit supply voltage [1] - 2.5 - 5.5 v center frequency - - 22.1184 - mhz +25 ; v dd =5 v -1 - +1 % calibrated internal oscillator frequency -40 ~+85 ; v dd =2.5 v~5.5 v -3 - +3 % operation current v dd =5 v - 500 - ua 7.3.4 internal 10 khz low speed oscillator parameter condition min. typ. max. unit supply voltage [1] - 2.5 - 5.5 v center frequency - - 10 - khz +25 ; v dd =5 v -30 - +30 % calibrated internal oscillator frequency -40 ~+85 ; v dd =2.5 v~5.5 v -50 - +50 % note: internal operation voltage comes from ldo. publication release date: jan. 2, 2012 - 74 - revision v2.03
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 75 - revision v2.03 7.4 analog characteristics 7.4.1 specification of 12-bit saradc symbol parameter min. typ. max. unit - resolution - - 12 bit dnl differential nonlinearity error - 3 - lsb inl integral nonlinearity error - 4 - lsb eo offset error - 1 10 lsb eg gain error (transfer gain) - 1 1.005 - - monotonic guaranteed fadc adc clock frequency (av dd =5v/3v) - - 16/8 mhz fs sample rate - - 600 k sps v dda supply voltage 3 - 5.5 v i dd - 0.5 - ma i dda supply current (avg.) - 1.5 - ma v ref reference voltage - v dda - v i ref reference current (avg.) - 1 - ma v in input voltage 0 - v ref v
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 76 - revision v2.03 7.4.2 specification of ldo and power management parameter min. typ. max. unit note input voltage 2.7 5 5.5 v v dd input voltage output voltage -10% 2.5 +10% v v dd > 2.7 v temperature -40 25 85 cbp - 1 - uf resr=1ohm note: 1. it is recommended that a 10uf or higher capacitor and a 100nf bypass capacitor are connected between v dd and the closest v ss pin of the device. 2. for ensuring power stability, a 1uf or higher capacit or must be connected between ldo pin and the closest v ss pin of the device.
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 77 - revision v2.03 7.4.3 specification of low voltage reset parameter condition min. typ. max. unit operation voltage - 1.7 - 5.5 v quiescent current v dd =5.5 v - - 5 ua temperature - -40 25 85 temperature=25 1.7 2.0 2.3 v temperature=-40 - 2.4 - v threshold voltage temperature=85 - 1.6 - v hysteresis - 0 0 0 v 7.4.4 specification of brown-out detector parameter condition min. typ. max. unit operation voltage - 2.5 - 5.5 v quiescent current av dd =5.5 v - - 125 a temperature - -40 25 85 bov_vl[1:0]=11 4.3 4.5 4.7 v bov_vl [1:0]=10 3.6 3.8 4.0 v bov_vl [1:0]=01 2.6 2.7 2.8 v brown-out voltage bov_vl [1:0]=00 2.1 2.2 2.3 v hysteresis - 30 - 150 mv 7.4.5 specification of power-on reset (5 v) parameter condition min. typ. max. unit temperature - -40 25 85 reset voltage v+ - 2 - v quiescent current vin>reset voltage - 1 - na
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 78 - revision v2.03 7.4.6 specification of temperature sensor parameter conditions min. typ. max. unit supply voltage [1] 2.5 - 5.5 v temperature -40 - 125 current consumption 6.4 - 10.5 ua gain -1.76 mv/ offset temp=0 720 mv note: internal operation voltage comes from ldo. 7.4.7 specification of comparator parameter condition min. typ. max. unit temperature - -40 25 85 v dd - 2.4 3 5.5 v v dd current 20 ua@v dd =3 v - 20 40 ua input offset voltage - - 5 15 mv output swing - 0.1 - v dd -0.1 v input common mode range - 0.1 - v dd -1.2 v dc gain - - 70 - db propagation delay @vcm=1.2 v and vdiff=0.1 v - 200 - ns comparison voltage 20 mv@vcm=1 v 50 mv@vcm=0.1 v 50 mv@vcm=v dd -1.2 @10 mv for non- hysteresis 10 20 - mv hysteresis one bit control w/o and w. hysteresis @vcm=0.4 v ~ v dd -1.2 v - 10 - mv wake-up time @cinp=1.3 v cinn=1.2 v - - 2 us
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 79 - revision v2.03 7.5 flash dc electrical characteristics symbol parameter conditions min. typ. max. unit n endu endurance 10000 cycles [1] t ret retention time temp=25 100 year t erase page erase time 20 40 ms t mass mass erase time 40 50 60 ms t prog program time 35 40 55 us v dd supply voltage 2.25 2.5 2.75 v [2] i dd1 read current 14 ma i dd2 program/erase current 7 ma i pd power down current 10 ua 1. number of program/erase cycles. 2. v dd is source from chip ldo output voltage. 3. this table is guaranteed by design, not test in production.
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 80 - revision v2.03 7.6 spi dynamic characteristics symbol parameter min. typ. max. unit spi master mode (v dd = 4.5v ~ 5.5v, 30pf loading capacitor) t ds data setup time 26 18 - ns t dh data hold time 0 - - ns t v data output valid time - 4 6 ns spi master mode (v dd = 3.0v ~ 3.6v, 30pf loading capacitor) t ds data setup time 39 26 - ns t dh data hold time 0 - - ns t v data output valid time - 6 10 ns spi slave mode (v dd = 4.5v ~ 5.5v, 30pf loading capacitor) t ds data setup time 0 - - ns t dh data hold time 2*pclk+4 - - ns t v data output valid time - 2*pclk+19 2*pclk+27 ns spi slave mode (v dd = 3.0v ~ 3.6v, 30pf loading capacitor) t ds data setup time 0 - - ns t dh data hold time 2*pclk+8 - - ns t v data output valid time - 2*pclk+27 2*pclk+40 ns
numicro? nuc100 data sheet figure 7-2 spi master dynamic characteristics timing figure 7-3 spi slave dynamic characteristics timing publication release date: jan. 2, 2012 - 81 - revision v2.03
numicro? nuc100 data sheet 8 package dimensions 8.1 100l lqfp (14x14x1.4 mm footprint 2.0mm) controlling dimension : millimeters 0.10 0 7 0 0.004 1.00 0.75 0.60 0.45 0.039 0.030 0.024 0.018 0.638 0.630 0.622 0.50 14.10 0.20 0.27 1.45 1.60 14.00 1.40 13.90 0.10 0.17 1.35 0.05 0.008 0.011 0.057 0.063 0.055 0.020 0.556 0.551 0.547 0.004 0.007 0.053 0.002 symbol min nom max max nom min dimension in inch dimension in mm a b c d e h d h e l y a1 a 2 l1 e 0.009 0.006 0.15 0.22 7 13.90 14.00 14.10 15.80 16.00 16.20 15.80 16.00 16.20 0.556 0.551 0.547 0.638 0.630 0.622 d d e e b a2 a1 a l1 e c l y h h 1 100 25 26 50 51 7 7 publication release date: jan. 2, 2012 - 82 - revision v2.03
numicro? nuc100 data sheet 8.2 64l lqfp (10x10x1.4mm footprint 2.0 mm) 0 7 0 1.00 0.75 0.60 12.00 0.45 0.039 0.030 0.024 0.472 0.018 0.50 0.20 0.27 1.45 1.60 10.00 1.40 0.09 0.17 1.35 0.05 0.008 0.011 0.057 0.063 0.393 0.055 0.020 0.004 0.007 0.053 0.002 symbol min nom max max nom min dimension in inch dimension in mm a b c d e h d h e l y 0 a a l 1 1 2 e 0.008 0.20 7 0.393 10.00 0.472 12.00 0.006 0.15 0.004 0.10 3.5 3.5 publication release date: jan. 2, 2012 - 83 - revision v2.03
numicro? nuc100 data sheet 8.3 48l lqfp (7x7x1.4mm footprint 2.0mm) publication release date: jan. 2, 2012 - 84 - revision v2.03
numicro? nuc100 data sheet publication release date: jan. 2, 2012 - 85 - revision v2.03 9 revision history version date page/ chap. description v1.00 march 1, 2010 - preliminary version initial issued v1.01 april 9, 2010 ch4 modify the block diagram v1.02 may 31, 2010 7.2 add operati on current of dc characteristics v1.03 aug. 23, 2010 7.2 modify oper ation current of dc characteristics v2.00 nov. 11, 2010 - update low density and selection table v2.01 may 6, 2011 - remove nuc130/nuc140 add spi dynamic characteristics remove tm0~3 of medium density remove word ?microwire? in all document v2.02 june 20, 2011 - modify temperature sensor spec revise pin description position for multi-function t2ex, t3ex, nrd, nwr update title of spi dy namic characteristics update bod spec v2.03 jan. 2, 2012 - 1. remove feature ?dynamic priority changing? for nvic 2. modify adc analog characteristic spec 3. revise the number of ua rt for nuc100 medium density selection table.
numicro? nuc100 data sheet important notice nuvoton products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. such applications are deemed, ?insecure usage?. insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for ve hicular use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life. all insecure usage shall be made at customer?s risk, and in the event that third parties lay claims to nuvoton as a result of customer?s insecure usage, customer shall indemnify the damages and liabilities thus incurred by nuvoton. publication release date: jan. 2, 2012 - 86 - revision v2.03

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